Re: [PATCH v7 1/1] vfio/nvgrace-gpu: Add Blackwell-Next GPU readiness check via CXL DVSEC

[Bjorn Helgaas]

On Thu, May 28, 2026 at 11:56:13AM -0600, Alex Williamson wrote:
> On Thu, 28 May 2026 09:38:40 +0000
> Ankit Agrawal <ankita@xxxxxxxxxx> wrote:
> ...
> >  drivers/vfio/pci/nvgrace-gpu/main.c | 144 ++++++++++++++++++++++++++--
> >  include/uapi/linux/pci_regs.h       |   1 +
> 
> Bjorn, I assume you don't object to this trivial addition:
> 
> > diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
> > index 14f634ab9350..718fb630f5bb 100644
> > --- a/include/uapi/linux/pci_regs.h
> > +++ b/include/uapi/linux/pci_regs.h
> > @@ -1357,6 +1357,7 @@
> >  #define  PCI_DVSEC_CXL_RANGE_SIZE_LOW(i)		(0x1C + (i * 0x10))
> >  #define   PCI_DVSEC_CXL_MEM_INFO_VALID			_BITUL(0)
> >  #define   PCI_DVSEC_CXL_MEM_ACTIVE			_BITUL(1)
> > +#define   PCI_DVSEC_CXL_MEM_ACTIVE_TIMEOUT		__GENMASK(15, 13)
> >  #define   PCI_DVSEC_CXL_MEM_SIZE_LOW			__GENMASK(31, 28)
> >  #define  PCI_DVSEC_CXL_RANGE_BASE_HIGH(i)		(0x20 + (i * 0x10))
> >  #define  PCI_DVSEC_CXL_RANGE_BASE_LOW(i)		(0x24 + (i * 0x10))

Yep, looks fine to me.