Re: [Patch v2 7/9] perf/x86/intel: Drop fixed-counter PEBS constraints for baseline PEBS

[Peter Zijlstra]

On Tue, Jun 09, 2026 at 01:02:20PM +0800, Dapeng Mi wrote:
> On SPR guests where pebs_baseline is not advertised, running:
> 
> $ ./perf record -e cpu/event=0x00,umask=0x01,i\
> 	 name=INST_RETIRED.PREC_DIST/p -c 10000 sleep 1
> 
> can trigger:
> 
> unchecked MSR access error: WRMSR to 0x3f1 ... in\
> 	 intel_pmu_pebs_enable_all()
> 
> Root cause:
> SPR-specific PEBS constraints allow fixed-counter scheduling,
> for example INST_RETIRED.PREC_DIST on fixed counter 0. In guests without
> pebs_baseline, KVM does not support PEBS sampling on fixed counters,
> so enabling such events reaches an invalid MSR programming path.
> 
> Fix:
> Drop fixed-counter entries from the PEBS constraint table. Without
> pebs_baseline, those fixed-counter PEBS events now resolve to empty
> constraints and are not scheduled/enabled, avoiding the warning and the
> broken guest PEBS path.
> 
> This is safe because, in pebs_baseline-capable cases, PEBS constraint
> lookup already falls back to non-PEBS constraints when needed, and
> fixed-counter constraints are effectively shared there.

I am confused, this works outside of KVM? (It appears to work fine on my
spr).. so removing this to fix some guest only issue seems wrong.


> Reported-by: Yi Lai <yi1.lai@xxxxxxxxx>
> Signed-off-by: Dapeng Mi <dapeng1.mi@xxxxxxxxxxxxxxx>
> ---
>  arch/x86/events/intel/ds.c | 13 -------------
>  1 file changed, 13 deletions(-)
> 
> diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
> index cb72af9b61ce..5db15a92017a 100644
> --- a/arch/x86/events/intel/ds.c
> +++ b/arch/x86/events/intel/ds.c
> @@ -1447,10 +1447,6 @@ struct event_constraint intel_skl_pebs_event_constraints[] = {
>  };
>  
>  struct event_constraint intel_icl_pebs_event_constraints[] = {
> -	INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x100000000ULL),	/* old INST_RETIRED.PREC_DIST */
> -	INTEL_FLAGS_UEVENT_CONSTRAINT(0x0100, 0x100000000ULL),	/* INST_RETIRED.PREC_DIST */
> -	INTEL_FLAGS_UEVENT_CONSTRAINT(0x0400, 0x800000000ULL),	/* SLOTS */
> -
>  	INTEL_PLD_CONSTRAINT(0x1cd, 0xff),			/* MEM_TRANS_RETIRED.LOAD_LATENCY */
>  	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf),	/* MEM_INST_RETIRED.STLB_MISS_LOADS */
>  	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf),	/* MEM_INST_RETIRED.STLB_MISS_STORES */
> @@ -1473,9 +1469,6 @@ struct event_constraint intel_icl_pebs_event_constraints[] = {
>  };
>  
>  struct event_constraint intel_glc_pebs_event_constraints[] = {
> -	INTEL_FLAGS_UEVENT_CONSTRAINT(0x100, 0x100000000ULL),	/* INST_RETIRED.PREC_DIST */
> -	INTEL_FLAGS_UEVENT_CONSTRAINT(0x0400, 0x800000000ULL),
> -
>  	INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xfe),
>  	INTEL_PLD_CONSTRAINT(0x1cd, 0xfe),
>  	INTEL_PSD_CONSTRAINT(0x2cd, 0x1),
> @@ -1500,9 +1493,6 @@ struct event_constraint intel_glc_pebs_event_constraints[] = {
>  };
>  
>  struct event_constraint intel_lnc_pebs_event_constraints[] = {
> -	INTEL_FLAGS_UEVENT_CONSTRAINT(0x100, 0x100000000ULL),	/* INST_RETIRED.PREC_DIST */
> -	INTEL_FLAGS_UEVENT_CONSTRAINT(0x0400, 0x800000000ULL),
> -
>  	INTEL_FLAGS_UEVENT_CONSTRAINT(0x012a, 0x1),		/* OCR.* events */
>  	INTEL_FLAGS_UEVENT_CONSTRAINT(0x012b, 0x1),		/* OCR.* events */
>  
> @@ -1534,9 +1524,6 @@ struct event_constraint intel_lnc_pebs_event_constraints[] = {
>  };
>  
>  struct event_constraint intel_pnc_pebs_event_constraints[] = {
> -	INTEL_FLAGS_UEVENT_CONSTRAINT(0x100, 0x100000000ULL),	/* INST_RETIRED.PREC_DIST */
> -	INTEL_FLAGS_UEVENT_CONSTRAINT(0x0400, 0x800000000ULL),
> -
>  	INTEL_HYBRID_LDLAT_CONSTRAINT(0x1cd, 0xfc),
>  	INTEL_HYBRID_STLAT_CONSTRAINT(0x2cd, 0x3),
>  	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf),	/* MEM_INST_RETIRED.STLB_MISS_LOADS */
> -- 
> 2.34.1
>