Re: [PATCH] media: mali-c55: Fix AEXP IHIST disable bit shift

[Dan Scally]

On 09/06/2026 07:42, Jacopo Mondi wrote:
> Hi David
>
> On Tue, Jun 09, 2026 at 06:32:31AM +0100, David Carlier wrote:
> > The post-Iridix auto-exposure histogram disable bit in
> > MALI_C55_REG_METERING_CONFIG is bit 16, but MALI_C55_AEXP_IHIST_DISABLE
> > was defined with a shift of 12, copied from the AEXP_HIST definition
> > above it. As the value is masked with the BIT(16) disable mask when it
> > is programmed, the result is always zero and the disable bit is never
> > set. The IHIST can therefore never be disabled, neither at ISP init nor
> > via a parameters block flagged V4L2_ISP_PARAMS_FL_BLOCK_DISABLE, and the
> > hardware keeps producing histogram statistics that userspace believes
> > are switched off.
> >
> > Use a shift of 16 so the disable request takes effect.
> >
> > Fixes: d5f281f3dd29 ("media: mali-c55: Add Mali-C55 ISP driver")
> > Cc: stable@xxxxxxxxxxxxxxx
> > Assisted-by: Claude:claude-opus-4-8
> > Signed-off-by: David Carlier <devnexen@xxxxxxxxx>
> > ---
> >   drivers/media/platform/arm/mali-c55/mali-c55-registers.h | 2 +-
> >   1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/media/platform/arm/mali-c55/mali-c55-registers.h b/drivers/media/platform/arm/mali-c55/mali-c55-registers.h
> > index f098effde..4cd13b702 100644
> > --- a/drivers/media/platform/arm/mali-c55/mali-c55-registers.h
> > +++ b/drivers/media/platform/arm/mali-c55/mali-c55-registers.h
> > @@ -173,7 +173,7 @@ enum mali_c55_interrupts {
> >   #define MALI_C55_AEXP_HIST_SWITCH_MASK			GENMASK(14, 13)
> >   #define MALI_C55_AEXP_HIST_SWITCH(x)			((x) << 13)
> >   #define MALI_C55_AEXP_IHIST_DISABLE_MASK		BIT(16)
> > -#define MALI_C55_AEXP_IHIST_DISABLE			(0x01 << 12)
> > +#define MALI_C55_AEXP_IHIST_DISABLE			(0x01 << 16)
>
> Thanks, this indeed was a bad copy and paste I presume
> Reviewed-by: Jacopo Mondi <jacopo.mondi@xxxxxxxxxxxxxxxx>

Yup, looks like it to me

Reviewed-by: Daniel Scally <dan.scally@xxxxxxxxxxxxxxxx>
> >   #define MALI_C55_AEXP_SRC_MASK				BIT(24)
> >
> >   #define MALI_C55_REG_TPG_CH0				0x18ed8
> > --
> > 2.53.0