Re: [PATCH 07/12] clk: qcom: gcc-mdm9607: Drop incorrect apss_tcu_clk_src

[Konrad Dybcio]

On 6/9/26 4:14 PM, Stephan Gerhold wrote:
> From: Stephan Gerhold <stephan@xxxxxxxxxxx>
> 
> This clock does not seem to exist on MDM9607. Reading/writing the registers
> always results in 0 or crashes. The math in the frequency table is also
> broken. GPLL2 on MDM9607 runs at 480 MHz, so:
> 
>  - F(155000000, P_GPLL2, 6, 0, 0), // 480 MHz/6 = 80 MHz, not 155 MHz
>  - F(310000000, P_GPLL2, 3, 0, 0), // 480 MHz/3 = 160 MHz, not 310 MHz
> 
> Presumably, this definition was mistakenly copied as-is from gcc-msm8916
> (which uses 930 MHz for GPLL2). There are no branch consumers of this root
> clock inside gcc-mdm9607 (notably, gcc_apss_tcu_clk has bimc_ddr_clk_src as
> parent instead of this clock), so we can just drop it.
> 
> Cc: stable@xxxxxxxxxxxxxxx
> Fixes: 48b7253264ea ("clk: qcom: Add MDM9607 GCC driver")
> Signed-off-by: Stephan Gerhold <stephan@xxxxxxxxxxx>
> ---

It does, CMD_RCGR @ 0x37000

Interestingly, there's also an SMMU instance.. although downstream doesn't
seem bothered with it

Konrad