Re: [PATCH v2 1/4] soc: qcom: rpmh: Allow non-child devices to issue write commands

[Dmitry Baryshkov]

On Thu, Jun 11, 2026 at 12:36:43PM +0200, Konrad Dybcio wrote:
> On 6/9/26 3:28 AM, Fenglin Wu wrote:
> > 
> > On 6/8/2026 5:21 AM, Dmitry Baryshkov wrote:
> >> On Thu, Jun 04, 2026 at 10:02:43AM +0800, Fenglin Wu wrote:
> >>> On 6/2/2026 3:29 PM, Fenglin Wu wrote:
> >>>> On 6/1/2026 9:37 PM, Dmitry Baryshkov wrote:
> >>>>> On Thu, May 28, 2026 at 06:05:35PM -0700, Fenglin Wu wrote:
> >>>>>> Currently, the RPMH driver only allows child devices of the RPMH
> >>>>>> controller to issue commands, as it assumes dev->parent points to the
> >>>>>> RSC device.
> >>>>>>
> >>>>>> There is a possibility that certain devices which are not children of
> >>>>>> the RPMH controller want to send commands for special control at the
> >>>>>> RPMH side. For example, in PMH0101 PMICs, there are bidirectional
> >>>>>> level shifter (LS) peripherals, and each LS works with a pair of PMIC
> >>>>>> GPIOs. The control of the LS, which is combined with the GPIO
> >>>>>> configuration, is handled by RPMH firmware for sharing the resource
> >>>>>> between different subsystems. From a hardware point of view, the LS
> >>>>>> functionality is tied to a pair of PMIC GPIOs, so its control is more
> >>>>>> suitable to be added in the pinctrl-spmi-gpio driver by adding the
> >>>>>> level-shifter function. However, the pinctrl-spmi-gpio device is a
> >>>>>> child device of the SPMI controller, not the RPMH controller.
> >>>>> This replicates the story of the PMIC regulators. There are two drivers,
> >>>>> one SPMI and one RPMh. Why don't we add a separate, RPMh-based GPIO
> >>>>> driver targeting only those paired GPIOs (and we don't even need to
> >>>>> represent them as a pair, it might be just one pin).
> >>>> Thanks for the suggestion.
> >>>>
> >>>> I agree that adding a separate, RPMh-based GPIO driver would be more
> >>>> straightforward from RPMh control perspective. It makes the new device
> >>>> as a child of the RSC device then it can naturally use the APIs for RPMh
> >>>> commands. The main challenge here is, we need to make the level-shifter
> >>>> mutually exclusive with other GPIO functions when the GPIO pairs are
> >>>> used in level-shifter function, which means we need to write SPMI
> >>>> commands to disable the associated GPIO modules. I am not sure if AOP
> >>>> already handles this; as far as I know, AOP only manages the
> >>>> BIDIR_LVL_SHIFTER module registers. Let me double check on this
> >>>> internally, if the GPIO modules could be controlled along
> >>>> with BIDIR_LVL_SHIFTER module registers at AOP side, and get back.
> >>>>
> >>> I checked on this internally, AOP only handles BIDIR_LVL_SHIFTER module
> >>> registers, it doesn't disable the associated GPIO modules. Also, I still
> >>> have no idea how could we make the "level-shifter" function to be mutually
> >>> exclusive with other GPIO functions after moved it into a separate driver.
> >>> Do you have further suggestions?
> >> So, for my understanding, we still need to write SPMI registers to
> >> configure the pins and only then AOP can handle the level shifter?
> >>
> >> I was thinking of using gpio-reserved-ranges to prevent those GPIOs from
> >> being used by the normal SPMI driver.
> > 
> > More background: "level-shifter" module is actually an independent hardware which is not part of the GPIO module. However, they are sharing the physical pins. Which means, from PMIC chip perspective, these pins can be configured to either a GPIO function or the "level-shifter" function. So in PMIC base dtsi file, for example, pmh0101.dtsi, these pins should not be restricted in the GPIO nodes in "gpio-reserved-ranges".
> > 
> > Also, we need to make the GPIO modules are disabled when the "level-shifter" is enabled, to ensure that the "level-shifter" circuitry is not impacted by the GPIO modules internal circuitry. So it is supposed to write GPIO EN_CTL register (offset 0x46) to 0 through SPMI bus when the "level-shifter" is enabled.
> > 
> > That's why we have the requirement to access both RPMh and SPMI bus in the same driver.
> 
> I was thinking about other ways to solve it.. maybe someting like:
> 
> &pmh0101_gpios {
> 	pmh0101_ls_pins1_2: foo-bar {
> 		pins = "gpio1", "gpio2";
> 		// appropriate pinctrl config
> 	};
> };
> 
> &rpmh_rsc {
> 	// should this be a gpio controller? a mux provider?
> 	// is there another class that would better suit this?
> 	rpmh_level_shifter: rpmh-foo-bar {
> 		pinctrl-0 = <&>;
> 		pinctrl-names = "default";
> 	};
> };
> 
> // but where would it make sense to describe?
> // fixed-regulator or something akin to that?
> &some_consumer {
> 	someclass = <&rpmh_level_shifter 1>;
> };
> 
> i.e. the "rpmh level shifter" driver would consume a reference to the
> pins, configure them as necessary (just like any other pinctrl consumer)
> upon request

SGTM.

> 
> Konrad

-- 
With best wishes
Dmitry