RE: [PATCH v5 2/4] arm64: dts: renesas: rzg3e-smarc-som: Add Versa3 clock generator

[John Madieu]

Hi Biju,

Thank you for your review.

> -----Original Message-----
> From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> Sent: mercredi 10 juin 2026 10:14
> To: John Madieu <john.madieu.xa@xxxxxxxxxxxxxx>; geert+renesas@xxxxxxxxx;
> magnus.damm <magnus.damm@xxxxxxxxx>; robh@xxxxxxxxxx; krzk+dt@xxxxxxxxxx;
> conor+dt@xxxxxxxxxx
> Subject: RE: [PATCH v5 2/4] arm64: dts: renesas: rzg3e-smarc-som: Add
> Versa3 clock generator
> 
> Hi John,
> 
> > -----Original Message-----
> > From: John Madieu <john.madieu.xa@xxxxxxxxxxxxxx>
> > Sent: 10 June 2026 08:47
> > Subject: [PATCH v5 2/4] arm64: dts: renesas: rzg3e-smarc-som: Add
> > Versa3 clock generator
> >
> > Add the Renesas 5P35023 (Versa3) programmable clock generator on the
> > I2C2 bus along with its 24MHz input clock (x2 oscillator) to feed the
> audio subsystem.
> >
> > The Versa3 provides the following clock outputs:
> > - Output 0: 24MHz (reference)
> > - Output 1: 12.288MHz (audio, 48kHz family)
> > - Output 2: 11.2896MHz (audio, 44.1kHz family)
> > - Output 3: 12.288MHz (audio)
> > - Output 4: 25MHz (DIFF1, Ethernet)
> >
> > These clocks are required for the audio codec and the Ethernet
> > controller found on the RZ/G3E SMARC EVK.
> >
> > Output 5 (DIFF2) is left out, as it is not connected on this board.
> >
> > Signed-off-by: John Madieu <john.madieu.xa@xxxxxxxxxxxxxx>
> > ---
> >
> > Changes:
> >
> > v5:
> >  - Drop Versa3 output 5 (DIFF2), as it is not connected.
> >  - Document output 4 (DIFF1) in the commit message; it is needed for
> >    Ethernet.
> >
> > v4: No changes
> > v3: No changes
> > v2: No changes
> >
> >  .../boot/dts/renesas/rzg3e-smarc-som.dtsi     | 20 +++++++++++++++++++
> >  1 file changed, 20 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
> > b/arch/arm64/boot/dts/renesas/rzg3e-
> > smarc-som.dtsi
> > index 15c22dbf0ad3..e951609d39e9 100644
> > --- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
> > @@ -78,6 +78,12 @@ reg_vdd0p8v_others: regulator-vdd0p8v-others {
> >  		regulator-always-on;
> >  	};
> >
> > +	x2: x2-clock {
> > +		compatible = "fixed-clock";
> > +		#clock-cells = <0>;
> > +		clock-frequency = <24000000>;
> > +	};
> > +
> >  	/* 32.768kHz crystal */
> >  	x3: x3-clock {
> >  		compatible = "fixed-clock";
> > @@ -137,6 +143,20 @@ raa215300: pmic@12 {
> >
> >  		interrupts-extended = <&pinctrl RZG3E_GPIO(S, 1)
> IRQ_TYPE_EDGE_FALLING>;
> >  	};
> > +
> > +	versa3: clock-generator@68 {
> > +		compatible = "renesas,5p35023";
> > +		reg = <0x68>;
> > +		#clock-cells = <1>;
> > +		clocks = <&x2>;
> > +
> > +		assigned-clocks = <&versa3 0>, <&versa3 1>,
> > +				  <&versa3 2>, <&versa3 3>,
> > +				  <&versa3 4>, <&versa3 5>;
> 
> No need to assign clock rate for unconnected output. So drop <&versa3 5>;

Noted.

> 
> > +		assigned-clock-rates = <24000000>, <12288000>,
> > +				       <11289600>, <12288000>,
> > +				       <25000000>, <25000000>;
> 
> 
> Drop <25000000>;

My bad. I missed that, these removal should have been handled in v5.
I'll address in v6.

Regards,
John