Re: [PATCH] pci: loongson: Avoid L0s on LS7A1000 PCIe x8 [0014:7a29] Root Ports rev2

[Huacai Chen]

On Thu, Jun 11, 2026 at 7:40 AM Xi Ruoyao <xry111@xxxxxxxxxxx> wrote:
>
> On Wed, 2026-06-10 at 16:21 +0800, Huacai Chen wrote:
> > Hi, Ruoyao,
> >
> > On Tue, Jun 9, 2026 at 11:26 PM Xi Ruoyao <xry111@xxxxxxxxxxx> wrote:
> > >
> > > Commit f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM states for
> > > devicetree platforms") has broke booting of a Loongson 3B4000 + 7A1000
> > > server with an Intel 750 Series SSD.  We also found a Loongson 3A5000
> > > board using the same 7A1000 bridge chip exhibiting the same issue with
> > > pcie_aspm=force and pcie_aspm.policy=powersave (ASPM is not enabled by
> > > default on the 3A5000 board because it's based on ACPI and the _OSC
> > > method has not been implemented in its DSDT/SSDT yet).
> > >
> > > This seems only affecting the 7A1000 chips shipping the revision 2 of
> > > the PCIe x8 Root Port: on other two boards with a (persumably older)
> > > LS7A1000 bridge chip utilizing the revision 1 of the root port, the
> > > issue does not reproduce.
> > Is that confirmed by chip designers?
>
> I don't have their contact.  This is based on our experiments on 5
> boards (two 3B4000 x 2 with rev2, one with rev1, one 3A4000 with rev1,
> one 3A5000 with rev2).
>
> > > Cc: Mingcong Bai <jeffbai@xxxxxxx>
> > > Cc: Henry Chen <chenx97@xxxxxxx>
> > > Cc: Han Gao <gaohan@xxxxxxxxxxx>
> > > Cc: Jiaxun Yang <jiaxun.yang@xxxxxxxxxxx>
> > > Fixes: f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM states for devicetree platforms")
> > > Signed-off-by: Xi Ruoyao <xry111@xxxxxxxxxxx>
> > > ---
> > >  drivers/pci/controller/pci-loongson.c | 13 +++++++++++++
> > >  1 file changed, 13 insertions(+)
> > >
> > > diff --git a/drivers/pci/controller/pci-loongson.c b/drivers/pci/controller/pci-loongson.c
> > > index a4250d7af1bf..dc7cee10643e 100644
> > > --- a/drivers/pci/controller/pci-loongson.c
> > > +++ b/drivers/pci/controller/pci-loongson.c
> > > @@ -212,6 +212,19 @@ static void loongson_pci_bridge_speed_quirk(struct pci_dev *pdev)
> > >  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON, 0x3c19, loongson_pci_bridge_speed_quirk);
> > >  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON, 0x3c29, loongson_pci_bridge_speed_quirk);
> > >
> > > +/*
> > > + * Some devices, for example Intel 750 Series SSD, experiences data loss
> > > + * (read timeout) on LS7A1000 PCIe x8 Root Port when ASPM L0s is enabled.
> > > + * This seems only affecting the revision 2.
> > > + */
> > > +static void ls7a_pcie_port2_aspm_quirk(struct pci_dev *pdev)
> > It is better to follow the namings in this file, i.e.
> > loongson_pcie_port2_aspm_quirk, or loongson_pcie_aspm_quirk for short.
>
> I'd keep "7a" in the name so in case another ASPM quirk is needed for
No need from my point of view, unless there is already another known issue.

Indeed, some other existing quirks are also for LS7A only but have no
7a in their names.

Huacai

> future products we'll not get a name clash.  Maybe
> loongson_7a_port2_aspm_quirk (I don't think _pcie_ is so useful here as
> the entire source file is for PCIe anyway).
>
>
> --
> Xi Ruoyao <xry111@xxxxxxxxxxx>