Re: [PATCH bpf-next v2 0/3] riscv, bpf: Fix signed operations and add 32 bit atomics

[Kuan-Wei Chiu]

Hi,

On Mon, May 11, 2026 at 10:16:45PM +0000, Kuan-Wei Chiu wrote:
> Fix miscompiled signed operations and expands 32 bit atomic support in
> the RV32 BPF JIT.
> 
> The current implementation ignores the instruction offset field used by
> the bpf instruction set to specify BPF_SDIV/BPF_SMOD and BPF_MOVSX.
> This causes these operations to be treated as unsigned or
> zero-extended, leading to test_bpf failures. Fix this by checking the
> offset and emitting the correct instructions.
> 
> Additionally, we leverage the mandatory A extension to natively support
> 32 bit bpf atomics (and, or, xor, xchg) by mapping them directly to
> amo*.w instructions. BPF_CMPXCHG continues to fall back to the
> interpreter.
> 
> As a result, test_bpf.ko now runs with 0 failures, and the total number
> of successfully JIT'ed test cases increases from 843 to 902.

Is there anything else I need to do for this patchset to land?

Regards,
Kuan-wei

> ---
> - Add missing Fixes tags.
> - Fix memory ordering by emitting aq=1, rl=1
> 
> Kuan-Wei Chiu (3):
>   riscv, bpf: Fix support for BPF_SDIV and BPF_SMOD in RV32 JIT
>   riscv, bpf: Fix support for BPF_MOVSX in RV32 JIT
>   riscv, bpf: Add 32 bit atomic operations to RV32 JIT
> 
>  arch/riscv/net/bpf_jit_comp32.c | 101 +++++++++++++++++++++++++++-----
>  1 file changed, 85 insertions(+), 16 deletions(-)
> 
> -- 
> 2.54.0.563.g4f69b47b94-goog
>