RE: [PATCH v6 1/3] dt-bindings: imx6q-pcie: Add optional intr/aer/pme interrupts for i.MX95

[Hongxing Zhu]

> -----Original Message-----
> From: Rob Herring <robh@xxxxxxxxxx>
> Sent: Friday, June 12, 2026 11:14 PM
> To: Hongxing Zhu (OSS) <hongxing.zhu@xxxxxxxxxxx>
> Cc: krzk+dt@xxxxxxxxxx; conor+dt@xxxxxxxxxx; bhelgaas@xxxxxxxxxx; Frank Li
> <frank.li@xxxxxxx>; l.stach@xxxxxxxxxxxxxx; lpieralisi@xxxxxxxxxx;
> kwilczynski@xxxxxxxxxx; mani@xxxxxxxxxx; s.hauer@xxxxxxxxxxxxxx;
> kernel@xxxxxxxxxxxxxx; festevam@xxxxxxxxx; linux-pci@xxxxxxxxxxxxxxx; linux-
> arm-kernel@xxxxxxxxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx;
> imx@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; Hongxing Zhu
> <hongxing.zhu@xxxxxxx>
> Subject: Re: [PATCH v6 1/3] dt-bindings: imx6q-pcie: Add optional intr/aer/pme
> interrupts for i.MX95
> 
> On Wed, Jun 03, 2026 at 02:25:08PM +0800, hongxing.zhu@xxxxxxxxxxx wrote:
> > From: Richard Zhu <hongxing.zhu@xxxxxxx>
> >
> > The i.MX95 PCIe controller introduces three additional dedicated
> > hardware interrupt lines for specific events:
> > - intr: general controller events
> > - aer: Advanced Error Reporting events
> > - pme: Power Management Events
> >
> > These interrupts are optional on i.MX95. PCIe basic functionality
> > (enumeration, configuration, and data transfer) works correctly
> > without them, as the controller can operate using only the existing msi
> interrupt.
> >
> > Earlier i.MX PCIe variants (imx6q, imx6sx, imx6qp, imx7d, imx8mm,
> > imx8mp, imx8mq, imx8q) do not have these three dedicated interrupt lines.
> >
> > Update the binding to allow up to 5 interrupts for i.MX95, while
> > restricting earlier variants to a maximum of 2 interrupts using
> > conditional constraints (if/then schema). This ensures the schema
> > accurately reflects the hardware capabilities of each SoC variant.
> >
> > Signed-off-by: Richard Zhu <hongxing.zhu@xxxxxxx>
> > Reviewed-by: Frank Li <Frank.Li@xxxxxxx>
> > ---
> >  .../bindings/pci/fsl,imx6q-pcie.yaml          | 29 +++++++++++++++++++
> >  1 file changed, 29 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > index e8b8131f5f23..9b5d4e59dfff 100644
> > --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > @@ -58,12 +58,18 @@ properties:
> >      items:
> >        - description: builtin MSI controller.
> >        - description: builtin DMA controller.
> > +      - description: PCIe event interrupt.
> > +      - description: builtin AER SPI standalone interrupt line.
> > +      - description: builtin PME SPI standalone interrupt line.
> >
> >    interrupt-names:
> >      minItems: 1
> >      items:
> >        - const: msi
> >        - const: dma
> > +      - const: intr
> > +      - const: aer
> > +      - const: pme
> >
> >    reset-gpio:
> >      deprecated: true
> > @@ -248,6 +254,29 @@ allOf:
> >              - const: pcie_aux
> >              - const: ref
> >              - const: extref  # Optional
> > +        interrupts:
> > +          maxItems: 5
> > +        interrupt-names:
> > +          maxItems: 5
> 
> 5 is already the max.
Thank you for the review.
You're correct. These maxItems constraints are redundant and will be removed
later.

Best Regards
Richard Zhu
> 
> > +
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          enum:
> > +            - fsl,imx6q-pcie
> > +            - fsl,imx6sx-pcie
> > +            - fsl,imx6qp-pcie
> > +            - fsl,imx7d-pcie
> > +            - fsl,imx8mm-pcie
> > +            - fsl,imx8mp-pcie
> > +            - fsl,imx8mq-pcie
> > +            - fsl,imx8q-pcie
> > +    then:
> > +      properties:
> > +        interrupts:
> > +          maxItems: 2
> > +        interrupt-names:
> > +          maxItems: 2
> >
> >  unevaluatedProperties: false
> >
> > --
> > 2.34.1
> >