[PATCH v5 net-next 0/2] Add multilink SERDES configuration support

[Gokul Praveen]

Add multilink SERDES configuration support on TI J784S4 SoC.

This patch series enables multilink SERDES configurations that require
different clock speeds for different links on TI J784S4 SoC.

For multilink SERDES configurations where the links require different
clock speeds (e.g., USXGMII+SGMII), all three clocks (refclk,
pll1_refclk, and phy_en_refclk) are needed. USXGMII requires a clock
speed of 156.25 MHz while SGMII requires 100 MHz. Since one reference
clock (refclk) alone cannot cater to these different clock speed
requirements, the second input reference clock (pll1_refclk) along with
phy_en_refclk is also needed.

Patch 1 updates the dt-bindings to support all three clocks by increasing
the maxItems to 3 and updating the clock-names parameter to allow both
pll1_refclk and phy_en_refclk to be used simultaneously.

Patch 2 adds the PLL1 refclk to the J784S4 SERDES nodes (SERDES0, SERDES1,
SERDES2, and SERDES4) as the assigned clocks parameter already references
PLL1 but the clocks parameter list was incomplete, causing multilink 
configuration failures.

Boot logs:
https://gist.github.com/GokulPraveen2001/7a09cc5ed0151d264f32cbbc31896605

Gokul Praveen (2):
  dt-bindings: phy: cadence-torrent: Update property values to support
    multilink SERDES configuration
  arm64: dts: ti: Add PLL1 refclk to J784S4 SoC SERDES node

 .../devicetree/bindings/phy/phy-cadence-torrent.yaml     | 3 ++-
 arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi | 9 ++++++---
 arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi               | 3 ++-
 3 files changed, 10 insertions(+), 5 deletions(-)

-- 
2.34.1