Re: [RESEND PATCH v4 01/15] x86/resctrl: Support Privilege Level Zero Association (PLZA)

[Borislav Petkov]

On Wed, Jul 08, 2026 at 11:55:30AM -0500, Babu Moger wrote:
> > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> > index 1b4a48bff18f..bf6fc71f87fa 100644
> > --- a/arch/x86/include/asm/cpufeatures.h
> > +++ b/arch/x86/include/asm/cpufeatures.h
> > @@ -517,6 +517,7 @@
> >   						      * and purposes if CLEAR_CPU_BUF_VM is set).
> >   						      */
> >   #define X86_FEATURE_X2AVIC_EXT		(21*32+20) /* AMD SVM x2AVIC support for 4k vCPUs */
> > +#define X86_FEATURE_PLZA		(21*32+21) /* Privilege Level Zero Association */
> >   /*
> >    * BUG word(s)
> > diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
> > index 937129ce6a96..1fa4d5aef17e 100644
> > --- a/arch/x86/kernel/cpu/scattered.c
> > +++ b/arch/x86/kernel/cpu/scattered.c
> > @@ -61,6 +61,7 @@ static const struct cpuid_bit cpuid_bits[] = {
> >   	{ X86_FEATURE_BMEC,			CPUID_EBX,  3, 0x80000020, 0 },
> >   	{ X86_FEATURE_ABMC,			CPUID_EBX,  5, 0x80000020, 0 },
> >   	{ X86_FEATURE_SDCIAE,			CPUID_EBX,  6, 0x80000020, 0 },
> > +	{ X86_FEATURE_PLZA,			CPUID_EBX,  9, 0x80000020, 0 },
> >   	{ X86_FEATURE_TSA_SQ_NO,		CPUID_ECX,  1, 0x80000021, 0 },
> >   	{ X86_FEATURE_TSA_L1_NO,		CPUID_ECX,  2, 0x80000021, 0 },
> >   	{ X86_FEATURE_AMD_WORKLOAD_CLASS,	CPUID_EAX, 22, 0x80000021, 0 },
> 
> Sashiko reported:
> 
> --- Patch [1]: [RESEND PATCH v4 01/15] x86/resctrl: Support Privilege Level
> Zero Association (PLZA) ---
> commit 0f2aa093b81d7a2e0dc203ce3466562f708898df
> Author: Babu Moger <babu.moger@xxxxxxx>
> x86/resctrl: Support Privilege Level Zero Association (PLZA)
> This commit adds support for AMD's Privilege Level Zero Association (PLZA)
> feature. It detects the feature via CPUID_Fn80000020_EBX_x00 [Bit 9] and
> adds the corresponding feature flag to the x86 cpufeatures array.
> Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 # [2]
> > diff --git a/arch/x86/include/asm/cpufeatures.h
> b/arch/x86/include/asm/cpufeatures.h
> > index 1b4a48bff18f7..bf6fc71f87fab 100644
> > --- a/arch/x86/include/asm/cpufeatures.h
> > +++ b/arch/x86/include/asm/cpufeatures.h
> > @@ -517,6 +517,7 @@
> >  						      * and purposes if CLEAR_CPU_BUF_VM is set).
> >  						      */
> >  #define X86_FEATURE_X2AVIC_EXT		(21*32+20) /* AMD SVM x2AVIC support for
> 4k vCPUs */
> > +#define X86_FEATURE_PLZA		(21*32+21) /* Privilege Level Zero Association
> */
> Should this addition also be mirrored in the tools directory copies of
> cpufeatures.h and kcpuid.csv?
> If tools/arch/x86/include/asm/cpufeatures.h is not updated to match, tools
> like
> perf can generate build warnings during check-headers.sh verification. Also,
> without updating tools/arch/x86/kcpuid/cpuid.csv, the kcpuid tool will be
> unaware of the new PLZA feature bit when users query CPU capabilities.
> 
> 
> I thought tools/arch/x86/include/asm/cpufeatures.h would be synced after the
> changes to arch/x86/include/asm/cpufeatures.h are merged. Has that process
> changed?

I guess that hasn't changed:

tools/include/uapi/README

Let's add those perf tools hackers to confirm.

> If the expectation is to update tools/arch/x86/include/asm/cpufeatures.h as
> part of this patch, I can add those changes as well.

-- 
Regards/Gruss,
    Boris.

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