[PATCH v1 00/11] Add support for StarFive JHB100 SFC

From: Changhuang Liang

Date: Thu Jul 09 2026 - 02:26:20 EST


This serial add support for the StarFive JHB100 SoC SPI Flash
Controller (SFC), which is based on the Synopsys DesignWare SSI
version 2.00a but with some customizations and it also add
enhanced SPI for DesignWare SPI controllers.

I picked up some patches from series [1].
This series depends on the series [2]:

[1] https://lore.kernel.org/all/20221212180732.79167-1-sudip.mukherjee@xxxxxxxxxx/
[2] https://lore.kernel.org/all/20260521012932.24163-1-changhuang.liang@xxxxxxxxxxxxxxxx/

The expected SFC device tree configuration is as follows:

sfc0_filter_syscon: syscon@14090000 {
compatible = "starfive,jhb100-sfc-filter-syscon", "syscon";
reg = <0x0 0x14090000 0x0 0x1000>;
};

sfc0: spi@18000000 {
compatible = "starfive,jhb100-sfc";
reg = <0x0 0x18000000 0x0 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <111>;
clocks = <&per1crg JHB100_PER1CLK_MAIN_ICG_EN_SFC0>;
resets = <&per1crg JHB100_PER1RST_MAIN_RSTN_SFC0>;
reset-names = "spi";
starfive,sfc-filter-syscon = <&sfc0_filter_syscon>;
num-cs = <2>;
status = "disabled";
};

I will send a new version of series [2] to add the sfc0_filter_syscon node.

Changhuang Liang (2):
spi: dt-bindings: snps,dw-apb-ssi: Add starfive,jhb100-sfc
spi: dw: Add support for StarFive JHB100 SoC SFC

Sudip Mukherjee (9):
spi: dw: Introduce spi_frf and STD_SPI
spi: dw: update NDF while using enhanced spi mode
spi: dw: update SPI_CTRLR0 register
spi: dw: add check for support of enhanced spi
spi: dw: Introduce enhanced single/dual/quad/octal spi
spi: dw: send cmd and addr to start the spi transfer
spi: dw: use irq handler for enhanced spi
spi: dw: adjust size of mem_op
spi: dw: detect enhanced spi mode

.../bindings/spi/snps,dw-apb-ssi.yaml | 22 ++
drivers/spi/spi-dw-core.c | 344 +++++++++++++++++-
drivers/spi/spi-dw-mmio.c | 42 +++
drivers/spi/spi-dw.h | 52 ++-
4 files changed, 450 insertions(+), 10 deletions(-)

--
2.25.1