Re: [PATCH v5 net-next 1/2] dt-bindings: phy: cadence-torrent: Update property values to support multilink SERDES configuration

[Conor Dooley]

On Thu, Jul 09, 2026 at 03:37:15PM +0530, Praveen, Gokul wrote:
> Hi Conor,
> 
> On 08-07-2026 22:09, Conor Dooley wrote:
> > On Wed, Jul 08, 2026 at 02:07:24PM +0530, Gokul Praveen wrote:
> > > Update the maxItems value of clocks parameter as 3 clocks
> > > (refclk,pll1_refclk,phy_en_refclk) are supported.
> > > 
> > > Update the clock-names parameter to support mutilink SERDES configuration
> > > as the existing enum configuration of the clock-names parameter does not
> > > allow both pll1_refclk and phy_en_refclk to be used at the same time,
> > > hence preventing the support for the configuration  (refclk,pll1_refclk,
> > > phy_en_refclk), which is neeed for multilink SERDES usecases.
> > > 
> > > For multilink SERDES configurations where the links require different
> > > clock speeds, all 3 clocks(refclk, pll1_refclk and phy_en_refclk)
> > > are needed.
> > > 
> > > For example,considering the USXGMII+SGMII multilink SERDES configuration
> > > usecase, having only 1 reference clock(refclk) fails because USXGMII
> > > requires a clock speed of 156.25 Mhz and SGMII protocol requires an
> > > clock speed of 100 Mhz.
> > > 
> > > Since one reference clock(refclk) alone cannot cater to the 2
> > > different clock speed requirements of these protocols, the second
> > > input reference clock(pll1_refclk) along with phy_en_refclk
> > > is also needed.
> > This binding supports 2 devices and the generic compatible. Do all these
> > devices have the new refclk?
> 
> Not all of these devices have the new refclk(pll1_refclk), Conor, which is
> is why the enum was kept as it is and in these devices multilink serdes
> configuration will not be possible due to the limitation of not having the
> new refclk(pll1_refclk).

In that case, please restrict 3 clocks to only the devices which have
them.

pw-bot: changes-requested

Thanks,
Conor.

> 
> However, The intent of this patch is to add multilink serdes support for the
> devices which have the new refclk because the
> 
> earlier clock-names configuration could not support having all the 3
> clocks(refclk, pll1_refclk, phy_en_refclk) in the clock-names, which is
> needed for mutlilink serdes configuration configuration.
> 
> Also, Please feel free to ask if you have any other queries, Conor and thank
> you for this query .
> 
> Thanks and Best Regards
> 
> Gokul Praveen
> 
> > Thanks,
> > Conor.
> > 
> > > Signed-off-by: Gokul Praveen <g-praveen@xxxxxx>
> > > ---
> > >   Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml | 3 ++-
> > >   1 file changed, 2 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> > > index 9af39b33646a..ac0f625cd76d 100644
> > > --- a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> > > +++ b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> > > @@ -34,7 +34,7 @@ properties:
> > >     clocks:
> > >       minItems: 1
> > > -    maxItems: 2
> > > +    maxItems: 3
> > >       description:
> > >         PHY input reference clocks - refclk (for PLL0) & pll1_refclk (for PLL1).
> > >         pll1_refclk is optional and used for multi-protocol configurations requiring
> > > @@ -48,6 +48,7 @@ properties:
> > >       items:
> > >         - const: refclk
> > >         - enum: [ pll1_refclk, phy_en_refclk ]
> > > +      - const: phy_en_refclk
> > >     reg:
> > >       minItems: 1
> > > -- 
> > > 2.34.1
> > >

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