[PATCH 0/7] dmaengine: dw-edma: Fixes and interrupt-path groundwork

[Koichiro Den]

Hi,

This series collects fixes and interrupt-path groundwork for dw-edma,
mostly split out of v1 of the "Support dynamic LL appends" series:

  [PATCH 00/17] dmaengine: dw-edma: Support dynamic LL appends
  https://lore.kernel.org/dmaengine/20260615154111.2174161-1-den@xxxxxxxxxxxxx/

That series had grown too large to review as one unit. Patches 1-4 are
what remains of v1's patches 01-05, slightly reordered but unchanged
in substance: Frank picked up v1's patch 01 (the residue fix) into
edma_ll v5,

  https://lore.kernel.org/dmaengine/20260709-edma_ll-v5-10-e199053d4300@xxxxxxx/

so it is no longer carried here. Patches 5-7 are new. None of them
depend on the dynamic-append work, and they are worth having on their
own.

Patches 1-4 are fixes.

- Patch 1 fixes a swapped argument order in the HDMA channel status
  register access (Cc: stable). v1 deferred this to a similar fix
  expected from Devendra, which has not appeared so far. Patch 1
  applies directly to mainline and can be picked independently.
- Patch 2 stops invoking completion callbacks for STOP-terminated
  descriptors.
- Patch 3 fixes vchan descriptor bookkeeping on termination.
- Patch 4 serializes channel state checks in pause/resume/terminate
  (carries Frank's Reviewed-by from the v1 thread).

Patch 5 drops a redundant remove-time pci_free_irq_vectors(): the device
is managed by pcim_enable_device(), so the vectors are released on
device release.

Patch 6 reads the shared DONE/ABORT interrupt status register once per
v0 handler pass. On remote setups every register read is a non-posted
round trip across the PCIe link, so the redundant reads cost real
latency in the hot path.

Patch 7 moves per-channel interrupt handling out of hard IRQ context
into per-channel work items on a dedicated WQ_UNBOUND | WQ_HIGHPRI
workqueue. On SoCs like R-Car S4 the endpoint-side eDMA raises a single
fixed SPI hardwired to CPU0 for all read and write channels; handling
every channel event in that hard IRQ serializes completion processing on
one CPU and turns vc.lock contention into system-wide interrupt latency.

Based on v7.2-rc1 (dmaengine/master).

To maintainers/reviewers:
- Sashiko's pre-existing-issue report on Frank's edma_ll v5 thread
  (lockless pause/resume/terminate_all racing the virt-dma lists,
  https://lore.kernel.org/dmaengine/20260709154606.734B31F00A3A@xxxxxxxxxxxxxxx/)
  is addressed by patch 4 of this series.
- This series textually conflicts with Frank's edma_ll v5 in the v0
  interrupt handler and the termination paths, but the conflicts are
  small. It has been tested with edma_ll v5 applied on top, on an R-Car
  S4 endpoint/host pair, and I am happy to rebase either way if
  preferred.
- The "Support dynamic LL appends" v2 and a follow-up v0 engine
  recovery series will follow shortly. They build on top of this
  series plus whichever revision of Frank's edma_ll lands.

Best regards,
Koichiro


Koichiro Den (7):
  dmaengine: dw-edma: Fix HDMA channel status register access
  dmaengine: dw-edma: Terminate STOP requests without callbacks
  dmaengine: dw-edma: Clean up vchan descriptors on termination
  dmaengine: dw-edma: Serialize channel state checks
  dmaengine: dw-edma-pcie: Drop redundant pci_free_irq_vectors()
  dmaengine: dw-edma: Snapshot the v0 interrupt status once per handler
    pass
  dmaengine: dw-edma: Defer channel IRQ handling to workqueue

 drivers/dma/dw-edma/dw-edma-core.c    | 170 +++++++++++++++++++++++---
 drivers/dma/dw-edma/dw-edma-core.h    |  12 ++
 drivers/dma/dw-edma/dw-edma-pcie.c    |   3 -
 drivers/dma/dw-edma/dw-edma-v0-core.c |  28 ++---
 drivers/dma/dw-edma/dw-hdma-v0-core.c |   2 +-
 5 files changed, 177 insertions(+), 38 deletions(-)

-- 
2.51.0