[PATCH] arm64/mm: Rename PGD_SIZE as PGD_TABLE_SIZE

[Anshuman Khandual]

PXD_SIZE represents the virtual address range size covered by a single page
table entry on a given page table level. On arm64 PGD entry address span is
represented with PGDIR_XXX macros instead while PGD_SIZE has been referring
to size of the PGD table itself. So PGD_SIZE has been some what confusing.

Rename PGD_SIZE as PGD_TABLE_SIZE making it explicit that it represents PGD
table size rather than virtual address range covered by a single PGD entry.
While here, also move PGD_TABLE_SIZE inside pgtable-hwdef.h header.

No functional change.

Cc: Catalin Marinas <catalin.marinas@xxxxxxx>
Cc: Will Deacon <will@xxxxxxxxxx>
Cc: Ryan Roberts <ryan.roberts@xxxxxxx>
Cc: David Hildenbrand (Arm) <david@xxxxxxxxxx>
Cc: linux-arm-kernel@xxxxxxxxxxxxxxxxxxx
Cc: linux-kernel@xxxxxxxxxxxxxxx
Signed-off-by: Anshuman Khandual <anshuman.khandual@xxxxxxx>
---
 arch/arm64/include/asm/pgalloc.h       | 2 --
 arch/arm64/include/asm/pgtable-hwdef.h | 1 +
 arch/arm64/mm/mmu.c                    | 2 +-
 arch/arm64/mm/pgd.c                    | 6 +++---
 4 files changed, 5 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/include/asm/pgalloc.h b/arch/arm64/include/asm/pgalloc.h
index 1b4509d3382c..d81df17663ee 100644
--- a/arch/arm64/include/asm/pgalloc.h
+++ b/arch/arm64/include/asm/pgalloc.h
@@ -17,8 +17,6 @@
 #define __HAVE_ARCH_PUD_FREE
 #include <asm-generic/pgalloc.h>
 
-#define PGD_SIZE	(PTRS_PER_PGD * sizeof(pgd_t))
-
 #if CONFIG_PGTABLE_LEVELS > 2
 
 static inline void __pud_populate(pud_t *pudp, phys_addr_t pmdp, pudval_t prot)
diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h
index 72f31800c703..241fc749455d 100644
--- a/arch/arm64/include/asm/pgtable-hwdef.h
+++ b/arch/arm64/include/asm/pgtable-hwdef.h
@@ -83,6 +83,7 @@
 #define PGDIR_SIZE		(_AC(1, UL) << PGDIR_SHIFT)
 #define PGDIR_MASK		(~(PGDIR_SIZE-1))
 #define PTRS_PER_PGD		(1 << (VA_BITS - PGDIR_SHIFT))
+#define PGD_TABLE_SIZE		(PTRS_PER_PGD * sizeof(pgd_t))
 
 /*
  * Contiguous page definitions.
diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c
index a25d8beacc83..bd9330fef173 100644
--- a/arch/arm64/mm/mmu.c
+++ b/arch/arm64/mm/mmu.c
@@ -1356,7 +1356,7 @@ static int __init map_entry_trampoline(void)
 	pgprot_val(prot) &= ~PTE_NG;
 
 	/* Map only the text into the trampoline page table */
-	memset(tramp_pg_dir, 0, PGD_SIZE);
+	memset(tramp_pg_dir, 0, PGD_TABLE_SIZE);
 	early_create_pgd_mapping(tramp_pg_dir, pa_start, TRAMP_VALIAS,
 				 entry_tramp_text_size(), prot,
 				 pgd_pgtable_alloc_init_mm, NO_BLOCK_MAPPINGS);
diff --git a/arch/arm64/mm/pgd.c b/arch/arm64/mm/pgd.c
index bf5110b91e2f..4f7c6416158b 100644
--- a/arch/arm64/mm/pgd.c
+++ b/arch/arm64/mm/pgd.c
@@ -19,7 +19,7 @@ static struct kmem_cache *pgd_cache __ro_after_init;
 
 static bool pgdir_is_page_size(void)
 {
-	if (PGD_SIZE == PAGE_SIZE)
+	if (PGD_TABLE_SIZE == PAGE_SIZE)
 		return true;
 	if (CONFIG_PGTABLE_LEVELS == 4)
 		return !pgtable_l4_enabled();
@@ -56,12 +56,12 @@ void __init pgtable_cache_init(void)
 	 * With 52-bit physical addresses, the architecture requires the
 	 * top-level table to be aligned to at least 64 bytes.
 	 */
-	BUILD_BUG_ON(!IS_ALIGNED(PGD_SIZE, 64));
+	BUILD_BUG_ON(!IS_ALIGNED(PGD_TABLE_SIZE, 64));
 #endif
 
 	/*
 	 * Naturally aligned pgds required by the architecture.
 	 */
-	pgd_cache = kmem_cache_create("pgd_cache", PGD_SIZE, PGD_SIZE,
+	pgd_cache = kmem_cache_create("pgd_cache", PGD_TABLE_SIZE, PGD_TABLE_SIZE,
 				      SLAB_PANIC, NULL);
 }
-- 
2.43.0