[PATCH v9 5/7] clk: qcom: tcsrcc-glymur: Add Mahua QREF regulator support
From: Qiang Yu
Date: Tue Jul 14 2026 - 01:01:50 EST
Mahua is based on Glymur but uses a different QREF topology, requiring
distinct regulator lists and clock descriptors for its PCIe clock
references.
Add mahua-specific regulator arrays and clk descriptor table, and use
match_data to select the correct descriptor table per compatible string at
probe time.
Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxxxxxxxx>
Signed-off-by: Qiang Yu <qiang.yu@xxxxxxxxxxxxxxxx>
---
drivers/clk/qcom/tcsrcc-glymur.c | 136 ++++++++++++++++++++++++++++++++++++++-
1 file changed, 133 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/qcom/tcsrcc-glymur.c b/drivers/clk/qcom/tcsrcc-glymur.c
index e0b545258ba4..1791e23739ed 100644
--- a/drivers/clk/qcom/tcsrcc-glymur.c
+++ b/drivers/clk/qcom/tcsrcc-glymur.c
@@ -12,6 +12,11 @@
#include <dt-bindings/clock/qcom,glymur-tcsr.h>
+struct tcsrcc_glymur_data {
+ const struct qcom_clk_ref_desc * const *descs;
+ size_t num_descs;
+};
+
static const char * const glymur_tcsr_tx0_rx5_regulators[] = {
"vdda-refgen3-0p9",
"vdda-refgen3-1p2",
@@ -56,6 +61,43 @@ static const char * const glymur_tcsr_tx1_rpt34_rx4_regulators[] = {
"vdda-qrefrx4-0p9",
};
+static const char * const mahua_tcsr_tx1_rpt01_rx1_regulators[] = {
+ "vdda-refgen3-0p9",
+ "vdda-refgen3-1p2",
+ "vdda-qreftx1-0p9",
+ "vdda-qrefrpt0-0p9",
+ "vdda-qrefrpt1-0p9",
+ "vdda-qrefrx1-0p9",
+};
+
+static const char * const mahua_tcsr_tx1_rpt012_rx2_regulators[] = {
+ "vdda-refgen3-0p9",
+ "vdda-refgen3-1p2",
+ "vdda-qreftx1-0p9",
+ "vdda-qrefrpt0-0p9",
+ "vdda-qrefrpt1-0p9",
+ "vdda-qrefrpt2-0p9",
+ "vdda-qrefrx2-0p9",
+};
+
+static const char * const mahua_tcsr_tx1_rpt0_rx0_regulators[] = {
+ "vdda-refgen3-0p9",
+ "vdda-refgen3-1p2",
+ "vdda-qreftx1-0p9",
+ "vdda-qrefrpt0-0p9",
+ "vdda-qrefrx0-0p9",
+};
+
+static const char * const mahua_tcsr_tx1_rpt345_rx3_regulators[] = {
+ "vdda-refgen3-0p9",
+ "vdda-refgen3-1p2",
+ "vdda-qreftx1-0p9",
+ "vdda-qrefrpt3-0p9",
+ "vdda-qrefrpt4-0p9",
+ "vdda-qrefrpt5-0p9",
+ "vdda-qrefrx3-0p9",
+};
+
static const struct regmap_config tcsr_cc_glymur_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
@@ -145,17 +187,105 @@ static const struct qcom_clk_ref_desc * const tcsr_cc_glymur_clk_descs[] = {
},
};
+static const struct qcom_clk_ref_desc * const tcsr_cc_mahua_clk_descs[] = {
+ [TCSR_EDP_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
+ .name = "tcsr_edp_clkref_en",
+ .offset = 0x60,
+ .regulator_names = mahua_tcsr_tx1_rpt0_rx0_regulators,
+ .num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt0_rx0_regulators),
+ },
+ [TCSR_PCIE_2_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
+ .name = "tcsr_pcie_2_clkref_en",
+ .offset = 0x4c,
+ .regulator_names = mahua_tcsr_tx1_rpt01_rx1_regulators,
+ .num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt01_rx1_regulators),
+ },
+ [TCSR_PCIE_3_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
+ .name = "tcsr_pcie_3_clkref_en",
+ .offset = 0x54,
+ .regulator_names = mahua_tcsr_tx1_rpt012_rx2_regulators,
+ .num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt012_rx2_regulators),
+ },
+ [TCSR_PCIE_4_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
+ .name = "tcsr_pcie_4_clkref_en",
+ .offset = 0x58,
+ .regulator_names = mahua_tcsr_tx1_rpt012_rx2_regulators,
+ .num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt012_rx2_regulators),
+ },
+ [TCSR_USB2_1_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
+ .name = "tcsr_usb2_1_clkref_en",
+ .offset = 0x6c,
+ .regulator_names = mahua_tcsr_tx1_rpt345_rx3_regulators,
+ .num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt345_rx3_regulators),
+ },
+ [TCSR_USB2_2_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
+ .name = "tcsr_usb2_2_clkref_en",
+ .offset = 0x70,
+ .regulator_names = mahua_tcsr_tx1_rpt345_rx3_regulators,
+ .num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt345_rx3_regulators),
+ },
+ [TCSR_USB2_3_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
+ .name = "tcsr_usb2_3_clkref_en",
+ .offset = 0x74,
+ .regulator_names = mahua_tcsr_tx1_rpt345_rx3_regulators,
+ .num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt345_rx3_regulators),
+ },
+ [TCSR_USB2_4_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
+ .name = "tcsr_usb2_4_clkref_en",
+ .offset = 0x88,
+ .regulator_names = mahua_tcsr_tx1_rpt0_rx0_regulators,
+ .num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt0_rx0_regulators),
+ },
+ [TCSR_USB3_0_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
+ .name = "tcsr_usb3_0_clkref_en",
+ .offset = 0x64,
+ .regulator_names = mahua_tcsr_tx1_rpt345_rx3_regulators,
+ .num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt345_rx3_regulators),
+ },
+ [TCSR_USB3_1_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
+ .name = "tcsr_usb3_1_clkref_en",
+ .offset = 0x68,
+ .regulator_names = mahua_tcsr_tx1_rpt345_rx3_regulators,
+ .num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt345_rx3_regulators),
+ },
+ [TCSR_USB4_1_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
+ .name = "tcsr_usb4_1_clkref_en",
+ .offset = 0x44,
+ },
+ [TCSR_USB4_2_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
+ .name = "tcsr_usb4_2_clkref_en",
+ .offset = 0x5c,
+ .regulator_names = mahua_tcsr_tx1_rpt01_rx1_regulators,
+ .num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt01_rx1_regulators),
+ },
+};
+
+static const struct tcsrcc_glymur_data tcsr_cc_glymur_data = {
+ .descs = tcsr_cc_glymur_clk_descs,
+ .num_descs = ARRAY_SIZE(tcsr_cc_glymur_clk_descs),
+};
+
+static const struct tcsrcc_glymur_data tcsr_cc_mahua_data = {
+ .descs = tcsr_cc_mahua_clk_descs,
+ .num_descs = ARRAY_SIZE(tcsr_cc_mahua_clk_descs),
+};
+
static const struct of_device_id tcsr_cc_glymur_match_table[] = {
- { .compatible = "qcom,glymur-tcsr" },
+ { .compatible = "qcom,glymur-tcsr", .data = &tcsr_cc_glymur_data },
+ { .compatible = "qcom,mahua-tcsr", .data = &tcsr_cc_mahua_data },
{ }
};
MODULE_DEVICE_TABLE(of, tcsr_cc_glymur_match_table);
static int tcsr_cc_glymur_probe(struct platform_device *pdev)
{
+ const struct tcsrcc_glymur_data *data = device_get_match_data(&pdev->dev);
+
+ if (!data)
+ return -ENODEV;
+
return qcom_clk_ref_probe(pdev, &tcsr_cc_glymur_regmap_config,
- tcsr_cc_glymur_clk_descs,
- ARRAY_SIZE(tcsr_cc_glymur_clk_descs));
+ data->descs, data->num_descs);
}
static struct platform_driver tcsr_cc_glymur_driver = {
--
2.34.1