Re: [PATCH v4 0/2] RISC-V IOMMU HPM support

[Chen Pei]

On Tue, Jul 14, 2026 at 01:36:20AM -0700, Zong Li wrote:
> This series implements support for the RISC-V IOMMU hardware performance
> monitor.
>
> The RISC-V IOMMU PMU driver is implemented as an auxiliary device driver
> created by the parent RISC-V IOMMU driver. Therefore, the child driver
> can obtain resources and information from the parent device, such as
> the MMIO base address and IRQ number.

I tested this series on QEMU and it works as expected.

Test setup:
 - Base: v7.2-rc2, both patches applied cleanly.
 - Kernel: rv64 defconfig with CONFIG_RISCV_IOMMU=y, CONFIG_RISCV_IOMMU_PCI=y,
   CONFIG_RISCV_IOMMU_PMU=y and CONFIG_PERF_EVENTS=y.
 - QEMU 10.2.0: -M virt,aia=aplic-imsic -device riscv-iommu-pci
   (hpm-counters=31).

Results:
 - The RISC-V IOMMU probes, the auxiliary device is created and the PMU
   driver registers successfully:
     riscv_iommu_pmu ...: Registered with 32 counters
 - The PMU shows up under
   /sys/bus/event_source/devices/riscv_iommu_pmu_<BDF> with the expected
   9 events (cycle, untranslated_req, translated_req, ats_trans_req,
   tlb_miss, dd_walk, pd_walk, s_vs_pt_walks, g_pt_walks) and 7 format
   attributes; "perf list" enumerates all of them.
 - No oops/WARN/KASAN splat during boot or driver bring-up.

Tested-by: Chen Pei <cp0613@xxxxxxxxxxxxxxxxx>

Thanks,
Pei