RE: [PATCH v19 08/12] mmc: renesas_sdhi: Add RZ/G3L SDHI support

[Biju Das]

Hi Geert,

Thanks for the feedback.

> -----Original Message-----
> From: Geert Uytterhoeven <geert@xxxxxxxxxxxxxx>
> Sent: 14 July 2026 14:31
> Subject: Re: [PATCH v19 08/12] mmc: renesas_sdhi: Add RZ/G3L SDHI support
> 
> Hi Biju,
> 
> On Thu, 9 Jul 2026 at 21:29, Biju <biju.das.au@xxxxxxxxx> wrote:
> > From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> >
> > The RZ/G3L SoC (r9a08g046) has an SDHI controller with several
> > differences from existing platforms, requiring dedicated handling.
> >
> > Utilise the TMIO_MMC_HWADJ flag to identify controllers that carry a
> > second hardware adjustment register (SDm_SCC_HWADJ2 at offset 0x010).
> > When both TMIO_MMC_TUNING_DELAY and TMIO_MMC_HWADJ are set,
> > renesas_sdhi_set_hw_adjustment_delay() additionally programs HWADJ2
> > with 0x3FFF at 3.3 V and 0xFF at 1.8 V. A new RZG3L_SDHI_SCC_HWADJ4
> > register (offset 0x022) is also cleared at the start of tuning when
> > TMIO_MMC_INTERNAL_DIVIDER is set.
> >
> > Add a new version constant SDHI_VER_RZ_G3L_SDMMC (0xce10) and extend
> > renesas_sdhi_sdbuf_width() to handle it alongside the existing Gen3
> > variants.
> >
> > Introduce of_data_rzg3l with RZ/G3L-specific parameters: a wider
> > clk_mask of 0x200000200, a max_divider of 2048 (reflecting the 11-bit
> > divider), a dedicated rzg3l_scc_taps table, and all relevant
> > tmio_flags, including TMIO_MMC_INTERNAL_DIVIDER and TMIO_MMC_HWADJ.
> > Wire it to a new of_rzg3l_compatible entry using sdhi_quirks_rzg3l
> > (which sets fixed_addr_mode), and register the
> > "renesas,sdhi-r9a08g046" compatible string in the OF match table.
> >
> > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> > ---
> > v18->v19:
> >  * Update commit description.
> >  * Updated handling for clk divider.
> >  * Renamed TMIO_MMC_HWADJ2->TMIO_MMC_HWADJ to make it generic for
> >    hardware tuning delays
> >  * Dropped duplicate SH_MOBILE_SDHI_SCC_TMPPORT2 macro
> 
> Thanks for the update!
> 
> > --- a/drivers/mmc/host/renesas_sdhi_core.c
> > +++ b/drivers/mmc/host/renesas_sdhi_core.c
> 
> > @@ -234,7 +236,14 @@ static void renesas_sdhi_set_clock(struct tmio_mmc_host *host,
> >         }
> >
> >         clock = clk & CLK_CTL_DIV_MASK;
> > -       if (clock != CLK_CTL_DIV_MASK)
> > +       if (host->pdata->max_divider != SDHI_MAX_DIVIDER_DEFAULT) {
> > +               u64 tmp;
> > +
> > +               tmp = FIELD_GET(GENMASK(9, 8), clk);
> > +               clock |= FIELD_PREP(GENMASK(17, 16), tmp);
> 
> This fails to build on RZ/Five, due to missing #include <linux/bitfield.h>.
> 
> Oh, fixed in v20...

Yes, I remembered the bot build issues when I worked on v20 and added the missing header file.

Cheers,
Biju