Re: [PATCH 0/6] spi: add multi-CS and per-transfer lane mask support

[David Lechner]

On 7/14/26 5:29 AM, Nuno Sá wrote:
> On Tue, Jul 14, 2026 at 02:55:31AM -0300, Jonathan Santos wrote:
>> This series introduces two SPI subsystem features: per-transfer chipselect
>> masks and multi-CS device support. Together they address the multi-device
>> setup described in [1] and the limitation noted in [2], where no SPI
>> controller completely handles logical chip selects beyond the first one.
>>
>> The first part of the set addresses multi-CS support. Some SPI controllers
>> can assert multiple chip selects simultaneously, but the existing code
>> hardcoded CS index 0 in both spi_set_cs() and of_spi_parse_dt(),
>> preventing this from working.
>>
>> The second part addresses dynamic lane selection for STRIPE mode. In
>> SPI_MULTI_LANE_MODE_STRIPE, all available lanes are currently always
>> active. Some peripherals need to select a different subset of rx/tx lanes
>> per transfer. New fields are added to the spi_transfer struct to allow
>> drivers to specify which lanes to use for each transfer. The documentation
>> is also updated to describe this new behavior.
>>
>> [1]: https://lore.kernel.org/linux-iio/af0EGv172ZMl%2F6N5@xxxxxxxxxxxxxxxxxxxxxxxxxx/T/#t
>> [2]: https://lore.kernel.org/all/20250915183725.219473-1-jonas.gorski@xxxxxxxxx/
>>
>> Jonathan Santos (6):
>>   spi: support simultaneous assertion of multiple CS
>>   spi: add per-transfer CS mask
>>   spi: spi-engine-ex: Add support for multi-CS devices
>>   spi: Documentation: multiple-data-lanes: describe rx and tx lane mask
>>   spi: add rx and tx lane mask to spi_transfer struct
>>   spi: axi-spi-engine: add support for dynamic multi-lane selection
> 
> It would be nice to include an actual user for this in the series.

Agree.

For context, here is the scenario from [1] (with arrow directions fixed):

+---------------+                                                 
|     ADC 0     |                                                 
|               |                                                 
|        SYNC_IN|<--+---------------------------+                 
|          DRDY0|---|------------------------+  |                 
|               |   |                        |  |   +------------+
|          SCLK0|<--|------+                 |  |   |    HOST    |
|           SDI0|<--|------|--+              |  |   |            |
|            CS0|<--|------|--|-----------+  |  +---|ADC_SYNC    |
|          DOUT0|---|------|--|--------+  |  |      |            |
|               |   |      |  |        |  |  |      |            |
+---------------+   |      +--|--------|--|--|------|SCLK        |
                    |      |  +--------|--|--|------|MOSI        |
+---------------+   |      |  |        |  |  |      |            |
|     ADC 1     |   |      |  |        |  |  |      |            |
|               |   |      |  |        |  |  +----->|DRDY0       |
|        SYNC_IN|<--+      |  |        |  +---------|CS0         |
|          DRDY1|---|------|--|----+   +----------->|MISO0       |
|               |   |      |  |    |                |            |
|          SCLK1|<--|------+  |    |                |            |
|           SDI1|<--|------|--+    +--------------->|DRDY1       |
|            CS1|<--|------|--|---------------------|CS1         |
|          DOUT1|---|------|--|-------------------->|MISO1       |
|               |   |      |  |                     |            |
+---------------+   |      |  |                     | .          |
                    |      |  |                     | .          |
       ...          |      |  |                     | .          |
                    |      |  |                     |            |
+---------------+   |      |  |            +------->|DRDYN       |
|     ADC N     |   |      |  |            | +------|CSN         |
|               |   |      |  |            | | +--->|MISON       |
|        SYNC_IN|<--+      |  |            | | |    |            |
|          DRDYN|----------|--|------------+ | |    +------------+
|               |          |  |              | |                  
|          SCLKN|<---------+  |              | |                  
|           SDIN|<------------+              | |                  
|            CSN|<---------------------------+ |                  
|          DOUTN|------------------------------+                  
|               |                                                 
+---------------+  


And the proposed DT from the discussion in [1].

spi {
    #address-cells = <1>;
    #size-cells = <0>;

    adc@0 {
	compatible = "adi,adaq7768-1";
	reg = <0>, <1>, <2>, <3>;
        
        spi-rx-bus-width = <1>, <1>, <1>, <1>;

	/* other properties */
    };
};

As a refresher, the idea is that this is considered to be one big ADC
with more channels (for simultaneous sampling) even though it is
physically multiple chips. 

Currently, this series is treating CS selection and mutli-lane SPI line
selection as completely independent. However, clearly certain spi-rx-bus
lines are tightly coupled with certain CS lines.

To reflect that (and easier to use in peripheral drivers), I think we
could bake this correlation into the SPI core code.

So struct spi_device.rx_lane_map would become a 2-D array where the
first index is the logical CS (following the pattern of .chip_select)
and the second index is the existing one for the data lane.

The trivial implementation would be to assume that reg and spi-rx-bus-width
have the same length and there is just a 1-to-1 correspondence (first data
lane is associated with first CS, and so on).

And we could add a new DT property for more complex mappings (multiple
data lanes per CS or wires not connected in logical order). We probably
don't need to do that right now though if there are no expected users
at the moment.

Then we would only need to add the CS selection to struct spi_transfer
and the controller driver would just use the map to pick the correct
data lanes based on other parameters as it does now. (So no need to
add .rx_lane_mask to struct spi_transfer.)

This way, the ADC (SPI peripheral driver) can set 1 CS in order to
configure individual chips and then set all CS to read sample data.
And all of the data lane selection is all handled transparently between
the core SPI code and the SPI controller driver.

(And obviously everything above applies to tx too, I just wrote rx
everywhere to keep it shorter.)

> 
> - Nuno Sá
> 
>>
>>  Documentation/spi/multiple-data-lanes.rst |  30 ++++++
>>  drivers/spi/spi-axi-spi-engine.c          | 106 +++++++++++++++++-----
>>  drivers/spi/spi.c                         |  97 +++++++++++++++++---
>>  include/linux/spi/spi.h                   |  12 +++
>>  4 files changed, 206 insertions(+), 39 deletions(-)
>>
>>
>> base-commit: 093239070573637ad2b4cb56abc9c4c7ee109294
>> -- 
>> 2.34.1
>>