[PATCH v3 8/8] arm64: dts: renesas: rzg3s-smarc: Enable CAN-FD
From: Claudiu Beznea
Date: Tue Jul 14 2026 - 13:40:00 EST
From: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
The two CAN FD channels available on the Renesas RZ/G3S SoC are routed
through the Renesas SMARC Carrier II board when used with the Renesas
RZ/G3S SMARC Module.
The CAN transceiver on the Carrier II board has its standby pins connected
to GPIOs that are selected through the SW_GPIO_CAN_PMOD switches. By
default, these switches route the GPIOs to the PMOD interfaces.
Enable the CAN FD controller and its two available channels.
Reviewed-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
---
Changes in v3:
- none
Changes in v2:
- collected tags
.../boot/dts/renesas/rzg3s-smarc-switches.h | 12 +++++
arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 46 +++++++++++++++++++
2 files changed, 58 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h b/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h
index bbf908a5322c..198874ad9a65 100644
--- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h
+++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h
@@ -37,4 +37,16 @@
*/
#define SW_OPT_MUX4 SW_ON
+/*
+ * SW_GPIO_CAN_PMOD[x] switches' states:
+ * @SW_GPIO_CAN_PMOD1:
+ * SW_OFF - GPIO8 connected to CAN0_STB (position 1-2)
+ * SW_ON - GPIO8 connected to PMOD1 (position 2-3)
+ * @SW_GPIO_CAN_PMOD2:
+ * SW_OFF - GPIO9 connected to CAN1_STB (position 4-5)
+ * SW_ON - GPIO9 connected to PMOD1 (position 5-6)
+ */
+#define SW_GPIO_CAN_PMOD1 SW_ON
+#define SW_GPIO_CAN_PMOD2 SW_ON
+
#endif /* __RZG3S_SMARC_SWITCHES_H__ */
diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi
index 70af605168b0..2be684f55914 100644
--- a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi
@@ -68,6 +68,24 @@ codec_dai: simple-audio-card,codec {
};
};
+ can_transceiver0: can-phy0 {
+ compatible = "ti,tcan1042";
+ #phy-cells = <0>;
+ max-bitrate = <8000000>;
+#if SW_GPIO_CAN_PMOD1 == SW_OFF
+ standby-gpios = <&pinctrl RZG2L_GPIO(13, 0) GPIO_ACTIVE_HIGH>;
+#endif
+ };
+
+ can_transceiver1: can-phy1 {
+ compatible = "ti,tcan1042";
+ #phy-cells = <0>;
+ max-bitrate = <8000000>;
+#if SW_GPIO_CAN_PMOD2 == SW_OFF
+ standby-gpios = <&pinctrl RZG2L_GPIO(13, 1) GPIO_ACTIVE_HIGH>;
+#endif
+ };
+
vcc_sdhi1: regulator-vcc-sdhi1 {
compatible = "regulator-fixed";
regulator-name = "SDHI1 Vcc";
@@ -92,6 +110,22 @@ &audio_clk2 {
clock-frequency = <12288000>;
};
+&canfd {
+ pinctrl-0 = <&canfd_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ channel0 {
+ phys = <&can_transceiver0>;
+ status = "okay";
+ };
+
+ channel1 {
+ phys = <&can_transceiver1>;
+ status = "okay";
+ };
+};
+
&ehci0 {
dr_mode = "otg";
status = "okay";
@@ -171,6 +205,18 @@ audio_clock_pins: audio-clock {
input-enable;
};
+ canfd_pins: canfd {
+ can0_pins: can0 {
+ pinmux = <RZG2L_PORT_PINMUX(6, 1, 3)>, /* CAN0_TX */
+ <RZG2L_PORT_PINMUX(6, 2, 3)>; /* CAN0_RX */
+ };
+
+ can1_pins: can1 {
+ pinmux = <RZG2L_PORT_PINMUX(17, 0, 3)>, /* CAN1_TX */
+ <RZG2L_PORT_PINMUX(17, 1, 3)>; /* CAN1_RX */
+ };
+ };
+
key-1-gpio-hog {
gpio-hog;
gpios = <RZG2L_GPIO(18, 0) GPIO_ACTIVE_LOW>;
--
2.43.0