RE: [PATCH v2] PCI: imx6: Fix i.MX6Q/DL boot hang by separating PHY power and reference clock control
From: Hongxing Zhu (OSS)
Date: Tue Jul 14 2026 - 21:39:43 EST
> -----Original Message-----
> From: Francesco Dolcini <francesco@xxxxxxxxxx>
> Sent: Tuesday, July 14, 2026 8:51 PM
> To: bhelgaas@xxxxxxxxxx; Hongxing Zhu (OSS) <hongxing.zhu@xxxxxxxxxxx>;
> linux-pci@xxxxxxxxxxxxxxx; Hongxing Zhu <hongxing.zhu@xxxxxxx>
> Cc: Frank Li <frank.li@xxxxxxx>; l.stach@xxxxxxxxxxxxxx; lpieralisi@xxxxxxxxxx;
> kwilczynski@xxxxxxxxxx; mani@xxxxxxxxxx; robh@xxxxxxxxxx;
> s.hauer@xxxxxxxxxxxxxx; kernel@xxxxxxxxxxxxxx; festevam@xxxxxxxxx; linux-
> arm-kernel@xxxxxxxxxxxxxxxxxxx; imx@xxxxxxxxxxxxxxx; linux-
> kernel@xxxxxxxxxxxxxxx; regressions@xxxxxxxxxxxxxxx
> Subject: Re: [PATCH v2] PCI: imx6: Fix i.MX6Q/DL boot hang by separating PHY
> power and reference clock control
>
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>
> Hello,
>
> On Wed, Jul 08, 2026 at 11:59:27AM +0800, hongxing.zhu@xxxxxxxxxxx wrote:
> > From: Richard Zhu <hongxing.zhu@xxxxxxx>
> >
> > Commit 610fa91d9863 ("PCI: imx6: Assert PERST# before enabling
> > regulators") introduced a boot hang on i.MX6Q/DL variants by changing
> > the initialization sequence.
> >
> > The issue stems from coupling PHY power (TEST_PD) and reference clock
> > (REF_CLK_EN) control in imx6q_pcie_enable_ref_clk(). When these are
> > managed together, the timing between PHY power-up and reference clock
> > enablement cannot be properly controlled, leading to initialization
> > failures.
> >
> > Fix this by separating the two concerns:
> >
> > - Move PHY power control (TEST_PD) to imx6q_pcie_core_reset() where it
> > logically belongs with reset operations. This ensures PHY power state
> > is managed as part of the core reset sequence.
> >
> > - Update imx6qp_pcie_core_reset() to call imx6q_pcie_core_reset() for
> > shared PHY power management, avoiding code duplication.
> >
> > - Make imx6q_pcie_enable_ref_clk() responsible only for reference clock
> > (REF_CLK_EN) control, simplifying its purpose.
> >
> > - Remove the 10us delay workaround from imx6q_pcie_enable_ref_clk() as
> > proper sequencing is now handled by the core_reset functions.
> >
> > This refactoring ensures PHY power is controlled during reset
> > operations, fixing the boot hang while improving code maintainability.
> >
> > Fixes: 610fa91d9863 ("PCI: imx6: Assert PERST# before enabling
> > regulators")
> > Signed-off-by: Richard Zhu <hongxing.zhu@xxxxxxx>
>
> What's the plan with this? 610fa91d9863 ("PCI: imx6: Assert PERST# before
> enabling regulators") introduces a severe regression with boards not booting at
> all.
>
> As of now we are not able to test anything, and our CI is completely blind on any
> other issue that linux 7.2 might have introduced.
>
> Is the plan to merge this, or to revert the commit? Any timeline?[]
Hi Francesco:
Sorry for this severe regression.
I prefer to merge this fix as soon as possible. Would you be able to test this
patch on your affected boards? Your testing would help expedite the merge
process and ensure the fix resolves the boot issue you're experiencing.
Thank you for your assistance.
Best Regards
Richard Zhu
>
> Francesco
>