[PATCH 2/3] clk: qcom: tcsrcc-x1e80100: Migrate to clk_ref helper
From: Qiang Yu
Date: Tue Jul 14 2026 - 22:41:51 EST
Replace local clk_branch-based clkref definitions with descriptor-based
registration via qcom_clk_ref_probe().
This keeps the x1e80100 driver focused on clock metadata and reuses
common runtime logic for regulator handling, enable/disable sequencing,
and OF provider wiring.
Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxxxxxxxx>
Signed-off-by: Qiang Yu <qiang.yu@xxxxxxxxxxxxxxxx>
---
drivers/clk/qcom/tcsrcc-x1e80100.c | 335 +++++++++++++------------------------
1 file changed, 113 insertions(+), 222 deletions(-)
diff --git a/drivers/clk/qcom/tcsrcc-x1e80100.c b/drivers/clk/qcom/tcsrcc-x1e80100.c
index 0b05c27b619b..ad1f6be83a53 100644
--- a/drivers/clk/qcom/tcsrcc-x1e80100.c
+++ b/drivers/clk/qcom/tcsrcc-x1e80100.c
@@ -5,252 +5,141 @@
*/
#include <linux/clk-provider.h>
+#include <linux/clk/qcom.h>
#include <linux/module.h>
+#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,x1e80100-tcsr.h>
-#include "clk-branch.h"
-#include "clk-regmap.h"
-#include "common.h"
-#include "reset.h"
-
-enum {
- DT_BI_TCXO_PAD,
+static const char * const x1e80100_tcsr_tx1_rpt0_rx0_regulators[] = {
+ "vdda-refgen0-0p9",
+ "vdda-refgen0-1p2",
+ "vdda-qreftx1-0p9",
+ "vdda-qreftx1-1p2",
+ "vdda-qrefrpt0-0p9",
+ "vdda-qrefrx0-0p9",
};
-static struct clk_branch tcsr_edp_clkref_en = {
- .halt_reg = 0x15130,
- .halt_check = BRANCH_HALT_DELAY,
- .clkr = {
- .enable_reg = 0x15130,
- .enable_mask = BIT(0),
- .hw.init = &(const struct clk_init_data) {
- .name = "tcsr_edp_clkref_en",
- .parent_data = &(const struct clk_parent_data){
- .index = DT_BI_TCXO_PAD,
- },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
- },
+static const char * const x1e80100_tcsr_tx1_rpt1_rx1_regulators[] = {
+ "vdda-refgen0-0p9",
+ "vdda-refgen0-1p2",
+ "vdda-qreftx1-0p9",
+ "vdda-qreftx1-1p2",
+ "vdda-qrefrpt1-0p9",
+ "vdda-qrefrx1-0p9",
};
-static struct clk_branch tcsr_pcie_2l_4_clkref_en = {
- .halt_reg = 0x15100,
- .halt_check = BRANCH_HALT_DELAY,
- .clkr = {
- .enable_reg = 0x15100,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "tcsr_pcie_2l_4_clkref_en",
- .parent_data = &(const struct clk_parent_data){
- .index = DT_BI_TCXO_PAD,
- },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
- },
+static const char * const x1e80100_tcsr_tx1_rpt12_rx2_regulators[] = {
+ "vdda-refgen0-0p9",
+ "vdda-refgen0-1p2",
+ "vdda-qreftx1-0p9",
+ "vdda-qreftx1-1p2",
+ "vdda-qrefrpt1-0p9",
+ "vdda-qrefrpt2-0p9",
+ "vdda-qrefrx2-0p9",
};
-static struct clk_branch tcsr_pcie_2l_5_clkref_en = {
- .halt_reg = 0x15104,
- .halt_check = BRANCH_HALT_DELAY,
- .clkr = {
- .enable_reg = 0x15104,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "tcsr_pcie_2l_5_clkref_en",
- .parent_data = &(const struct clk_parent_data){
- .index = DT_BI_TCXO_PAD,
- },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
- },
+static const char * const x1e80100_tcsr_tx0_rpt3_rx3_regulators[] = {
+ "vdda-refgen2-0p9",
+ "vdda-refgen2-1p2",
+ "vdda-qreftx0-0p9",
+ "vdda-qreftx0-1p2",
+ "vdda-qrefrpt3-0p9",
+ "vdda-qrefrx3-0p9",
};
-static struct clk_branch tcsr_pcie_8l_clkref_en = {
- .halt_reg = 0x15108,
- .halt_check = BRANCH_HALT_DELAY,
- .clkr = {
- .enable_reg = 0x15108,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "tcsr_pcie_8l_clkref_en",
- .parent_data = &(const struct clk_parent_data){
- .index = DT_BI_TCXO_PAD,
- },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
- },
+static const char * const x1e80100_tcsr_tx0_rpt4_rx4_regulators[] = {
+ "vdda-refgen2-0p9",
+ "vdda-refgen2-1p2",
+ "vdda-qreftx0-0p9",
+ "vdda-qreftx0-1p2",
+ "vdda-qrefrpt4-0p9",
+ "vdda-qrefrx4-0p9",
};
-static struct clk_branch tcsr_usb3_mp0_clkref_en = {
- .halt_reg = 0x1510c,
- .halt_check = BRANCH_HALT_DELAY,
- .clkr = {
- .enable_reg = 0x1510c,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "tcsr_usb3_mp0_clkref_en",
- .parent_data = &(const struct clk_parent_data){
- .index = DT_BI_TCXO_PAD,
- },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
- },
+static const struct regmap_config tcsr_cc_x1e80100_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x2f000,
+ .fast_io = true,
};
-static struct clk_branch tcsr_usb3_mp1_clkref_en = {
- .halt_reg = 0x15110,
- .halt_check = BRANCH_HALT_DELAY,
- .clkr = {
- .enable_reg = 0x15110,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "tcsr_usb3_mp1_clkref_en",
- .parent_data = &(const struct clk_parent_data){
- .index = DT_BI_TCXO_PAD,
- },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
+static const struct qcom_clk_ref_desc * const tcsr_cc_x1e80100_clk_descs[] = {
+ [TCSR_EDP_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
+ .name = "tcsr_edp_clkref_en",
+ .offset = 0x15130,
+ .regulator_names = x1e80100_tcsr_tx0_rpt3_rx3_regulators,
+ .num_regulators = ARRAY_SIZE(x1e80100_tcsr_tx0_rpt3_rx3_regulators),
},
-};
-
-static struct clk_branch tcsr_usb2_1_clkref_en = {
- .halt_reg = 0x15114,
- .halt_check = BRANCH_HALT_DELAY,
- .clkr = {
- .enable_reg = 0x15114,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "tcsr_usb2_1_clkref_en",
- .parent_data = &(const struct clk_parent_data){
- .index = DT_BI_TCXO_PAD,
- },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
+ [TCSR_PCIE_2L_4_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
+ .name = "tcsr_pcie_2l_4_clkref_en",
+ .offset = 0x15100,
+ .regulator_names = x1e80100_tcsr_tx1_rpt1_rx1_regulators,
+ .num_regulators = ARRAY_SIZE(x1e80100_tcsr_tx1_rpt1_rx1_regulators),
},
-};
-
-static struct clk_branch tcsr_ufs_phy_clkref_en = {
- .halt_reg = 0x15118,
- .halt_check = BRANCH_HALT_DELAY,
- .clkr = {
- .enable_reg = 0x15118,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "tcsr_ufs_phy_clkref_en",
- .parent_data = &(const struct clk_parent_data){
- .index = DT_BI_TCXO_PAD,
- },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
+ [TCSR_PCIE_2L_5_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
+ .name = "tcsr_pcie_2l_5_clkref_en",
+ .offset = 0x15104,
+ .regulator_names = x1e80100_tcsr_tx1_rpt12_rx2_regulators,
+ .num_regulators = ARRAY_SIZE(x1e80100_tcsr_tx1_rpt12_rx2_regulators),
},
-};
-
-static struct clk_branch tcsr_usb4_1_clkref_en = {
- .halt_reg = 0x15120,
- .halt_check = BRANCH_HALT_DELAY,
- .clkr = {
- .enable_reg = 0x15120,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "tcsr_usb4_1_clkref_en",
- .parent_data = &(const struct clk_parent_data){
- .index = DT_BI_TCXO_PAD,
- },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
+ [TCSR_PCIE_8L_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
+ .name = "tcsr_pcie_8l_clkref_en",
+ .offset = 0x15108,
+ .regulator_names = x1e80100_tcsr_tx1_rpt0_rx0_regulators,
+ .num_regulators = ARRAY_SIZE(x1e80100_tcsr_tx1_rpt0_rx0_regulators),
},
-};
-
-static struct clk_branch tcsr_usb4_2_clkref_en = {
- .halt_reg = 0x15124,
- .halt_check = BRANCH_HALT_DELAY,
- .clkr = {
- .enable_reg = 0x15124,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "tcsr_usb4_2_clkref_en",
- .parent_data = &(const struct clk_parent_data){
- .index = DT_BI_TCXO_PAD,
- },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
+ [TCSR_USB3_MP0_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
+ .name = "tcsr_usb3_mp0_clkref_en",
+ .offset = 0x1510c,
+ .regulator_names = x1e80100_tcsr_tx1_rpt0_rx0_regulators,
+ .num_regulators = ARRAY_SIZE(x1e80100_tcsr_tx1_rpt0_rx0_regulators),
},
-};
-
-static struct clk_branch tcsr_usb2_2_clkref_en = {
- .halt_reg = 0x15128,
- .halt_check = BRANCH_HALT_DELAY,
- .clkr = {
- .enable_reg = 0x15128,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "tcsr_usb2_2_clkref_en",
- .parent_data = &(const struct clk_parent_data){
- .index = DT_BI_TCXO_PAD,
- },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
+ [TCSR_USB3_MP1_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
+ .name = "tcsr_usb3_mp1_clkref_en",
+ .offset = 0x15110,
+ .regulator_names = x1e80100_tcsr_tx1_rpt0_rx0_regulators,
+ .num_regulators = ARRAY_SIZE(x1e80100_tcsr_tx1_rpt0_rx0_regulators),
},
-};
-
-static struct clk_branch tcsr_pcie_4l_clkref_en = {
- .halt_reg = 0x1512c,
- .halt_check = BRANCH_HALT_DELAY,
- .clkr = {
- .enable_reg = 0x1512c,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "tcsr_pcie_4l_clkref_en",
- .parent_data = &(const struct clk_parent_data){
- .index = DT_BI_TCXO_PAD,
- },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
+ [TCSR_USB2_1_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
+ .name = "tcsr_usb2_1_clkref_en",
+ .offset = 0x15114,
+ .regulator_names = x1e80100_tcsr_tx0_rpt3_rx3_regulators,
+ .num_regulators = ARRAY_SIZE(x1e80100_tcsr_tx0_rpt3_rx3_regulators),
+ },
+ [TCSR_UFS_PHY_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
+ .name = "tcsr_ufs_phy_clkref_en",
+ .offset = 0x15118,
+ .regulator_names = x1e80100_tcsr_tx1_rpt12_rx2_regulators,
+ .num_regulators = ARRAY_SIZE(x1e80100_tcsr_tx1_rpt12_rx2_regulators),
+ },
+ [TCSR_USB4_1_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
+ .name = "tcsr_usb4_1_clkref_en",
+ .offset = 0x15120,
+ .regulator_names = x1e80100_tcsr_tx0_rpt4_rx4_regulators,
+ .num_regulators = ARRAY_SIZE(x1e80100_tcsr_tx0_rpt4_rx4_regulators),
+ },
+ [TCSR_USB4_2_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
+ .name = "tcsr_usb4_2_clkref_en",
+ .offset = 0x15124,
+ .regulator_names = x1e80100_tcsr_tx0_rpt3_rx3_regulators,
+ .num_regulators = ARRAY_SIZE(x1e80100_tcsr_tx0_rpt3_rx3_regulators),
+ },
+ [TCSR_USB2_2_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
+ .name = "tcsr_usb2_2_clkref_en",
+ .offset = 0x15128,
+ .regulator_names = x1e80100_tcsr_tx0_rpt3_rx3_regulators,
+ .num_regulators = ARRAY_SIZE(x1e80100_tcsr_tx0_rpt3_rx3_regulators),
+ },
+ [TCSR_PCIE_4L_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
+ .name = "tcsr_pcie_4l_clkref_en",
+ .offset = 0x1512c,
+ .regulator_names = x1e80100_tcsr_tx0_rpt4_rx4_regulators,
+ .num_regulators = ARRAY_SIZE(x1e80100_tcsr_tx0_rpt4_rx4_regulators),
},
-};
-
-static struct clk_regmap *tcsr_cc_x1e80100_clocks[] = {
- [TCSR_EDP_CLKREF_EN] = &tcsr_edp_clkref_en.clkr,
- [TCSR_PCIE_2L_4_CLKREF_EN] = &tcsr_pcie_2l_4_clkref_en.clkr,
- [TCSR_PCIE_2L_5_CLKREF_EN] = &tcsr_pcie_2l_5_clkref_en.clkr,
- [TCSR_PCIE_8L_CLKREF_EN] = &tcsr_pcie_8l_clkref_en.clkr,
- [TCSR_USB3_MP0_CLKREF_EN] = &tcsr_usb3_mp0_clkref_en.clkr,
- [TCSR_USB3_MP1_CLKREF_EN] = &tcsr_usb3_mp1_clkref_en.clkr,
- [TCSR_USB2_1_CLKREF_EN] = &tcsr_usb2_1_clkref_en.clkr,
- [TCSR_UFS_PHY_CLKREF_EN] = &tcsr_ufs_phy_clkref_en.clkr,
- [TCSR_USB4_1_CLKREF_EN] = &tcsr_usb4_1_clkref_en.clkr,
- [TCSR_USB4_2_CLKREF_EN] = &tcsr_usb4_2_clkref_en.clkr,
- [TCSR_USB2_2_CLKREF_EN] = &tcsr_usb2_2_clkref_en.clkr,
- [TCSR_PCIE_4L_CLKREF_EN] = &tcsr_pcie_4l_clkref_en.clkr,
-};
-
-static const struct regmap_config tcsr_cc_x1e80100_regmap_config = {
- .reg_bits = 32,
- .reg_stride = 4,
- .val_bits = 32,
- .max_register = 0x2f000,
- .fast_io = true,
-};
-
-static const struct qcom_cc_desc tcsr_cc_x1e80100_desc = {
- .config = &tcsr_cc_x1e80100_regmap_config,
- .clks = tcsr_cc_x1e80100_clocks,
- .num_clks = ARRAY_SIZE(tcsr_cc_x1e80100_clocks),
};
static const struct of_device_id tcsr_cc_x1e80100_match_table[] = {
@@ -261,7 +150,9 @@ MODULE_DEVICE_TABLE(of, tcsr_cc_x1e80100_match_table);
static int tcsr_cc_x1e80100_probe(struct platform_device *pdev)
{
- return qcom_cc_probe(pdev, &tcsr_cc_x1e80100_desc);
+ return qcom_clk_ref_probe(pdev, &tcsr_cc_x1e80100_regmap_config,
+ tcsr_cc_x1e80100_clk_descs,
+ ARRAY_SIZE(tcsr_cc_x1e80100_clk_descs));
}
static struct platform_driver tcsr_cc_x1e80100_driver = {
--
2.34.1