Re: [PATCH v2] pci: loongson: Avoid L0s on LS7A1000 PCIe x8 [0014:7a29] Root Ports rev2

[Manivannan Sadhasivam]

On Wed, Jun 24, 2026 at 01:36:48AM +0800, Xi Ruoyao wrote:
> Commit f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM states for
> devicetree platforms") has broke booting of a Loongson 3B4000 + 7A1000
> server with an Intel 750 Series SSD.  We also found a Loongson 3A5000
> board using the same 7A1000 bridge chip exhibiting the same issue with
> pcie_aspm=force and pcie_aspm.policy=powersave (ASPM is not enabled by
> default on the 3A5000 board because it's based on ACPI and the _OSC
> method has not been implemented in its DSDT/SSDT yet).
> 
> This seems only affecting the 7A1000 chips shipping the revision 2 of
> the PCIe x8 Root Port: on other two boards with a (persumably older)
> LS7A1000 bridge chip utilizing the revision 1 of the root port, the
> issue does not reproduce.
> 

Can you share some error logs? In the comment below you mentioned "read
timeout", what does it correspond to?

Adding error logs in the patch description will help others experiencing the
same issue to find this patch.

- Mani

> Cc: Mingcong Bai <jeffbai@xxxxxxx>
> Cc: Henry Chen <chenx97@xxxxxxx>
> Cc: Han Gao <gaohan@xxxxxxxxxxx>
> Cc: Jiaxun Yang <jiaxun.yang@xxxxxxxxxxx>
> Fixes: f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM states for devicetree platforms")
> Signed-off-by: Xi Ruoyao <xry111@xxxxxxxxxxx>
> ---
> 
> Changes from v1: rename the quirk function into a style similar to other
> quirk functions in the same file.
> 
>  drivers/pci/controller/pci-loongson.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/drivers/pci/controller/pci-loongson.c b/drivers/pci/controller/pci-loongson.c
> index a4250d7af1bf..235b44859b53 100644
> --- a/drivers/pci/controller/pci-loongson.c
> +++ b/drivers/pci/controller/pci-loongson.c
> @@ -212,6 +212,19 @@ static void loongson_pci_bridge_speed_quirk(struct pci_dev *pdev)
>  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON, 0x3c19, loongson_pci_bridge_speed_quirk);
>  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON, 0x3c29, loongson_pci_bridge_speed_quirk);
>  
> +/*
> + * Some devices, for example Intel 750 Series SSD, experiences data loss
> + * (read timeout) on LS7A1000 PCIe x8 Root Port when ASPM L0s is enabled.
> + * This seems only affecting the revision 2.
> + */
> +static void loongson_port2_aspm_quirk(struct pci_dev *pdev)
> +{
> +	if (pdev->revision == 2)
> +		pcie_aspm_remove_cap(pdev, PCI_EXP_LNKCAP_ASPM_L0S);
> +}
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON, DEV_LS7A_PCIE_PORT2,
> +			 loongson_port2_aspm_quirk);
> +
>  static struct loongson_pci *pci_bus_to_loongson_pci(struct pci_bus *bus)
>  {
>  	struct pci_config_window *cfg;
> -- 
> 2.54.0
> 

-- 
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