Re: [Patch v2 0/7] perf/x86: Miscellaneous PMU bug fixes and optimizations

[Mi, Dapeng]

Hi Peter,

Not sure if you have bandwidth to review the patch-set? This patchset fixes
some recently found issues by Sashiko. Most of issues are error handling
related. Thanks.


On 7/13/2026 4:27 PM, Dapeng Mi wrote:
> Changes since v1:
> - Patch 3/7: Ensure cpuc->pmu is not the static pmu before calling
>   hybrid_pmu(cpuc->pmu) in intel_pmu_cpu_dead() (Sashiko).
>
> This series fixes recently found x86 core PMU bugs. Most of bugs are
> found by Sashiko in reviewing the "Support SIMD/eGPRs/SSP registers 
> sampling for perf" patch-set, e.g.,
> https://lore.kernel.org/all/20260706022123.480411F000E9@xxxxxxxxxxxxxxx/
> https://lore.kernel.org/all/20260706021852.DE2ED1F000E9@xxxxxxxxxxxxxxx/
>
> The last patch 7/7 optimizes ACR handling in match_prev_assignment() and
> mitigate the performance overhead.
>
> Tests:
> Below test cases are run on Diamonds and Novalake. No issues are found.
> - Perf stat test
>   $ perf test 119
> - Perf record tests 
>   $ perf test 155
> - Perf record LBR tests
>   $ perf test 156
>
> History:
> v1: https://lore.kernel.org/all/20260710065128.1799838-1-dapeng1.mi@xxxxxxxxxxxxxxx/
>
> Dapeng Mi (7):
>   perf/x86: Unregister PMI handler on PMU init failure
>   perf/x86: Free hybrid state on PMU init failure
>   perf/x86: Guard intel_pmu_cpu_dead() against invalid hybrid PMU casts
>   perf/x86/intel: Unwind cpuc state if PEBS buffer setup fails
>   perf/x86: Remove stale fixed counter helper and fix hybrid PMU access
>   perf/x86/intel: Fix intel_cap handling on hybrid PMUs
>   perf/x86: Optimize ACR handling in match_prev_assignment()
>
>  arch/x86/events/core.c       | 45 +++++++++++++++++++-------
>  arch/x86/events/intel/core.c | 61 ++++++++++++++++++++++++++----------
>  arch/x86/events/perf_event.h | 12 ++-----
>  3 files changed, 81 insertions(+), 37 deletions(-)
>
>
> base-commit: edda9051e267b7390c7ce24b1b71434414ad156e