Re: [PATCH v9 00/11] PCI/CXL: Add CXL reset support for Type 2 devices

[Alejandro Lucero Palau]

On 7/9/26 02:02, Srirangan Madhavan wrote:
> Hi folks!
>
> This series adds CXL Reset support for CXL Type 2 devices through the
> existing PCI reset_method ABI. The reset sequence follows the CXL 4.0
> specification [1], including CXL.cache disable, optional cache
> writeback, CXL Reset initiation, ResetComplete polling, and ResetError
> reporting.


Hi Srirangan,


I'm working on understanding all the implications in this patchset, and 
I have to say my mind is on adding multipf support to Type2 drivers, 
with a RFC coming soon to the list.


Some comments below.


Thanks.


> The userspace ABI is the existing PCI reset interface:
>
>      /sys/bus/pci/devices/.../reset_method
>      /sys/bus/pci/devices/.../reset


Not sure if this will be available in any device PFs, but I think it 
should only be available for PF0 as the specs define this function as 
the one having the CXL DVSEC. In any case, the reset will only be 
possible if PF0 is not attached to the Type2 driver and therefore the 
memdev is not there. With the multipf support that will also be the case 
as any none PF0 device will rely on PF0 CXL driver initialization and if 
PF0 is detached from the driver, so will it be for non PF0 devices.


Note this is not the same than the "Non-CXL Function Map DVSEC" you are 
checking later on.


<snip>

> The CPU cache invalidation step depends on
> cpu_cache_invalidate_memregion() support for the affected address ranges.
> If no runtime provider is available, the kernel emits a warning and
> continues after the affected HDM ranges have been reserved.


Because no memdev should be there this step should not be necessary. 
Maybe as a sanity check.