Re: [PATCH v4 04/21] pinctrl: starfive: Add StarFive JHB100 sys0 controller driver

[Changhuang Liang]

Hi, Philipp

Thanks for the review.

> On Sa, 2026-08-01 at 00:26 -0700, Changhuang Liang wrote:
> > Add pinctrl driver for StarFive JHB100 SoC System-0(sys0) pinctrl
> > controller.
> >
> > Simultaneously add a generic pinctrl driver framework for registering
> > the pinctrl of other domains (sys1, sys2, and so on) in the JHB100 SoC.
> >
> > Co-developed-by: Lianfeng Ouyang <lianfeng.ouyang@xxxxxxxxxxxxxxxx>
> > Signed-off-by: Lianfeng Ouyang <lianfeng.ouyang@xxxxxxxxxxxxxxxx>
> > Signed-off-by: Alex Soo <yuklin.soo@xxxxxxxxxxxxxxxx>
> > Signed-off-by: Changhuang Liang <changhuang.liang@xxxxxxxxxxxxxxxx>
> > ---
> >  MAINTAINERS                                   |    9 +
> >  drivers/pinctrl/starfive/Kconfig              |   20 +
> >  drivers/pinctrl/starfive/Makefile             |    3 +
> >  .../starfive/pinctrl-starfive-jhb100-sys0.c   |  119 ++
> >  .../starfive/pinctrl-starfive-jhb100.c        | 1456
> +++++++++++++++++
> >  .../starfive/pinctrl-starfive-jhb100.h        |  159 ++
> >  6 files changed, 1766 insertions(+)
> >  create mode 100644
> > drivers/pinctrl/starfive/pinctrl-starfive-jhb100-sys0.c
> >  create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jhb100.c
> >  create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jhb100.h
> >
> [...]
> > diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-sys0.c
> > b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-sys0.c
> > new file mode 100644
> > index 000000000000..ed23c0c43960
> > --- /dev/null
> > +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-sys0.c
> > @@ -0,0 +1,119 @@
> [...]
> > +int jhb100_pinctrl_probe(struct platform_device *pdev) {
> > +	struct device *dev = &pdev->dev;
> > +	struct gpio_irq_chip *girq;
> > +	const struct jhb100_pinctrl_domain_info *info;
> > +	struct jhb100_pinctrl *sfp;
> > +	struct pinctrl_desc *jhb100_pinctrl_desc;
> > +	const struct starfive_pinctrl_regs *pinctrl_regs;
> > +	struct reset_control *rst;
> > +	struct clk *clk;
> > +	int ret;
> > +
> > +	info = of_device_get_match_data(&pdev->dev);
> > +	if (!info)
> > +		return -ENODEV;
> > +
> > +	pinctrl_regs = info->regs;
> > +
> > +	sfp = devm_kzalloc(dev, sizeof(*sfp), GFP_KERNEL);
> > +	if (!sfp)
> > +		return -ENOMEM;
> > +
> > +	sfp->base = devm_platform_ioremap_resource(pdev, 0);
> > +	if (IS_ERR(sfp->base))
> > +		return PTR_ERR(sfp->base);
> > +
> > +	clk = devm_clk_get_optional_enabled(dev, NULL);
> > +	if (IS_ERR(clk))
> > +		return dev_err_probe(dev, PTR_ERR(clk), "could not get & enable
> > +clock\n");
> > +
> > +	rst = devm_reset_control_array_get_optional_shared(dev);
> 
> The dt-binding specifies a single reset control. Why does this use the array
> API?
> 
> Using devm_reset_control_get_optional_shared_deasserted() could simplify
> this a little bit.
> 

pinctrl_adc will have 2 reset lines, one of which will be shared with the ADC. 
Refer to the dts below, but it is not currently included in the current series.

			pinctrl_adc0: pinctrl@11bc2800 {
				compatible = "starfive,jhb100-pinctrl-adc0";
				resets = <&per2crg JHB100_PER2RST_ADC0_IOMUX_PRESETN>,
					 <&per2crg JHB100_PER2RST_ADC0_PRESETN>;
			};

			adc0: adc@11be1400 {
				compatible = "starfive,jhb100-adc";
				resets = <&per2crg JHB100_PER2RST_ADC0_PRESETN>;
			};

Best Regards,
Changhuang