[PATCH 2/5] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: clean up PCI function nodes
From: Alex Elder
Date: Fri Aug 07 2026 - 15:59:50 EST
The qcs6490-rb3gen2-industrial-mezzanine overlay defines two nodes
representing TC956x chips, each of which contains a PCIe switch and
an embedded endpoint that implements two PCIe functions.
The devicetree nodes erroneously include a "pci" device_type property
for the two PCIe functions. That property should only be used for a
PCI device "that implements a PCI bus". Remove this property for the
two function nodes.
In addition, these nodes define #address-cells, #size-cells, and ranges
properties, which are not normally defined for PCIe endpoints. Remove
properties as well; they can be added back once they are actually
needed/used.
Fixes: 4559b435f741b ("arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch node for PCIe0")
Signed-off-by: Alex Elder <elder@xxxxxxxxxxxx>
---
.../qcs6490-rb3gen2-industrial-mezzanine.dtso | 16 ----------------
1 file changed, 16 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
index 46bb52c667a4d..82c4d47fc2aaa 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
+++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
@@ -132,18 +132,10 @@ pcie@3,0 {
pcie@0,0 {
reg = <0x50000 0x0 0x0 0x0 0x0>;
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- ranges;
};
pcie@0,1 {
reg = <0x50100 0x0 0x0 0x0 0x0>;
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- ranges;
};
};
@@ -227,18 +219,10 @@ pcie@3,0 {
pcie@0,0 {
reg = <0x50000 0x0 0x0 0x0 0x0>;
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- ranges;
};
pcie@0,1 {
reg = <0x50100 0x0 0x0 0x0 0x0>;
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- ranges;
};
};
};
--
2.53.0