Re: [PATCH v3 3/6] dt-bindings: usb: add Altera Agilex5 DWC3 controller

[Krzysztof Kozlowski]

On Wed, Aug 12, 2026 at 03:32:56PM +0800, Adrian Ng Ho Yin wrote:
> +allOf:
> +  - $ref: snps,dwc3-common.yaml#
> +
> +properties:
> +  compatible:
> +    const: altr,agilex5-dwc3
> +
> +  reg:
> +    description: DWC3 USB3 controller register region.

Drop description, obvious.

> +    maxItems: 1
> +
> +  clocks:
> +    items:
> +      - description: Controller reference clock
> +      - description: Controller suspend clock
> +      - description: Master/Core bus clock
> +
> +  clock-names:
> +    items:
> +      - const: ref
> +      - const: suspend
> +      - const: bus_early

And the order of entries is taken from?

> +
> +  interrupts:
> +    maxItems: 1
> +
> +  phys:
> +    minItems: 2
> +    maxItems: 2
> +
> +  phy-names:
> +    items:
> +      - const: usb2-phy
> +      - const: usb3-phy
> +
> +  iommus:
> +    maxItems: 1
> +
> +  resets:
> +    description: Resets for the DWC3 core and its ECC block.

Drop description

> +    items:
> +      - description: DWC3 core reset
> +      - description: DWC3 ECC reset
> +
> +  reset-names:
> +    items:
> +      - const: dwc3

core

> +      - const: dwc3-ecc

ecc

Unless both names are coming from other schema?


> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - clock-names
> +  - interrupts
> +  - phys
> +  - phy-names
> +  - resets
> +  - reset-names

Best regards,
Krzysztof