Re: [PATCH v9 2/5] phy: qualcomm: hdmi-28lpm: provide dynamic configuration

From: Manivannan Sadhasivam

Date: Wed Aug 12 2026 - 09:56:16 EST

On Wed, May 13, 2026 at 09:14:05PM +0300, Dmitry Baryshkov wrote:
> Replace fixed value configuration tables with the values calculated at
> the runtime. In some cases the values might differ from the original
> values. Those were validated on the IFC6410 board.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxxxxxxxx>

One nit below. With that fixed,

Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxxxxxxxx>

> ---
> drivers/phy/qualcomm/phy-qcom-hdmi-28lpm.c | 325 +++++++++--------------------
> 1 file changed, 104 insertions(+), 221 deletions(-)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-hdmi-28lpm.c b/drivers/phy/qualcomm/phy-qcom-hdmi-28lpm.c
> index f1e7113e10bd..90d3331313c0 100644
> --- a/drivers/phy/qualcomm/phy-qcom-hdmi-28lpm.c
> +++ b/drivers/phy/qualcomm/phy-qcom-hdmi-28lpm.c
> @@ -148,222 +148,17 @@
>
> #define HDMI_8960_COMMON_DIV 5
>
> -struct pll_rate {
> - unsigned long rate;
> - int num_reg;
> - struct {
> - u32 val;
> - u32 reg;
> - } conf[32];
> -};
> -
> -/* NOTE: keep sorted highest freq to lowest: */
> -static const struct pll_rate freqtbl[] = {
> - { 154000000, 14, {
> - { 0x08, REG_HDMI_8960_PHY_PLL_REFCLK_CFG },
> - { 0x20, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 },
> - { 0xf9, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 },
> - { 0x02, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 },
> - { 0x03, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 },
> - { 0x3b, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 },
> - { 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3 },
> - { 0x86, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 },
> - { 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 },
> - { 0x0d, REG_HDMI_8960_PHY_PLL_SDM_CFG0 },
> - { 0x4d, REG_HDMI_8960_PHY_PLL_SDM_CFG1 },
> - { 0x5e, REG_HDMI_8960_PHY_PLL_SDM_CFG2 },
> - { 0x42, REG_HDMI_8960_PHY_PLL_SDM_CFG3 },
> - { 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG4 },
> - }
> - },
> - /* 1080p60/1080p50 case */
> - { 148500000, 27, {
> - { 0x02, REG_HDMI_8960_PHY_PLL_REFCLK_CFG },
> - { 0x02, REG_HDMI_8960_PHY_PLL_CHRG_PUMP_CFG },
> - { 0x01, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 },
> - { 0x33, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 },
> - { 0x2c, REG_HDMI_8960_PHY_PLL_IDAC_ADJ_CFG },
> - { 0x06, REG_HDMI_8960_PHY_PLL_I_VI_KVCO_CFG },
> - { 0x0a, REG_HDMI_8960_PHY_PLL_PWRDN_B },
> - { 0x76, REG_HDMI_8960_PHY_PLL_SDM_CFG0 },
> - { 0x01, REG_HDMI_8960_PHY_PLL_SDM_CFG1 },
> - { 0x4c, REG_HDMI_8960_PHY_PLL_SDM_CFG2 },
> - { 0xc0, REG_HDMI_8960_PHY_PLL_SDM_CFG3 },
> - { 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG4 },
> - { 0x9a, REG_HDMI_8960_PHY_PLL_SSC_CFG0 },
> - { 0x00, REG_HDMI_8960_PHY_PLL_SSC_CFG1 },
> - { 0x00, REG_HDMI_8960_PHY_PLL_SSC_CFG2 },
> - { 0x00, REG_HDMI_8960_PHY_PLL_SSC_CFG3 },
> - { 0x10, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG0 },
> - { 0x1a, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG1 },
> - { 0x0d, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2 },
> - { 0xe6, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 },
> - { 0x02, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 },
> - { 0x3b, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 },
> - { 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3 },
> - { 0x86, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 },
> - { 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 },
> - { 0x33, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG6 },
> - { 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG7 },
> - }
> - },
> - { 108000000, 13, {
> - { 0x08, REG_HDMI_8960_PHY_PLL_REFCLK_CFG },
> - { 0x21, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 },
> - { 0xf9, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 },
> - { 0x1c, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 },
> - { 0x02, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 },
> - { 0x3b, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 },
> - { 0x86, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 },
> - { 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 },
> - { 0x49, REG_HDMI_8960_PHY_PLL_SDM_CFG0 },
> - { 0x49, REG_HDMI_8960_PHY_PLL_SDM_CFG1 },
> - { 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG2 },
> - { 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG3 },
> - { 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG4 },
> - }
> - },
> - /* 720p60/720p50/1080i60/1080i50/1080p24/1080p30/1080p25 */
> - { 74250000, 8, {
> - { 0x0a, REG_HDMI_8960_PHY_PLL_PWRDN_B },
> - { 0x12, REG_HDMI_8960_PHY_PLL_REFCLK_CFG },
> - { 0x01, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 },
> - { 0x33, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 },
> - { 0x76, REG_HDMI_8960_PHY_PLL_SDM_CFG0 },
> - { 0xe6, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 },
> - { 0x02, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 },
> - { 0x3b, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 },
> - }
> - },
> - { 74176000, 14, {
> - { 0x18, REG_HDMI_8960_PHY_PLL_REFCLK_CFG },
> - { 0x20, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 },
> - { 0xf9, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 },
> - { 0xe5, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 },
> - { 0x02, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 },
> - { 0x3b, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 },
> - { 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3 },
> - { 0x86, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 },
> - { 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 },
> - { 0x0c, REG_HDMI_8960_PHY_PLL_SDM_CFG0 },
> - { 0x4c, REG_HDMI_8960_PHY_PLL_SDM_CFG1 },
> - { 0x7d, REG_HDMI_8960_PHY_PLL_SDM_CFG2 },
> - { 0xbc, REG_HDMI_8960_PHY_PLL_SDM_CFG3 },
> - { 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG4 },
> - }
> - },
> - { 65000000, 14, {
> - { 0x18, REG_HDMI_8960_PHY_PLL_REFCLK_CFG },
> - { 0x20, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 },
> - { 0xf9, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 },
> - { 0x8a, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 },
> - { 0x02, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 },
> - { 0x3b, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 },
> - { 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3 },
> - { 0x86, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 },
> - { 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 },
> - { 0x0b, REG_HDMI_8960_PHY_PLL_SDM_CFG0 },
> - { 0x4b, REG_HDMI_8960_PHY_PLL_SDM_CFG1 },
> - { 0x7b, REG_HDMI_8960_PHY_PLL_SDM_CFG2 },
> - { 0x09, REG_HDMI_8960_PHY_PLL_SDM_CFG3 },
> - { 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG4 },
> - }
> - },
> - /* 480p60/480i60 */
> - { 27030000, 18, {
> - { 0x0a, REG_HDMI_8960_PHY_PLL_PWRDN_B },
> - { 0x38, REG_HDMI_8960_PHY_PLL_REFCLK_CFG },
> - { 0x02, REG_HDMI_8960_PHY_PLL_CHRG_PUMP_CFG },
> - { 0x20, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 },
> - { 0xff, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 },
> - { 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG0 },
> - { 0x4e, REG_HDMI_8960_PHY_PLL_SDM_CFG1 },
> - { 0xd7, REG_HDMI_8960_PHY_PLL_SDM_CFG2 },
> - { 0x03, REG_HDMI_8960_PHY_PLL_SDM_CFG3 },
> - { 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG4 },
> - { 0x2a, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 },
> - { 0x03, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 },
> - { 0x3b, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 },
> - { 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3 },
> - { 0x86, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 },
> - { 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 },
> - { 0x33, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG6 },
> - { 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG7 },
> - }
> - },
> - /* 576p50/576i50 */
> - { 27000000, 27, {
> - { 0x32, REG_HDMI_8960_PHY_PLL_REFCLK_CFG },
> - { 0x02, REG_HDMI_8960_PHY_PLL_CHRG_PUMP_CFG },
> - { 0x01, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 },
> - { 0x33, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 },
> - { 0x2c, REG_HDMI_8960_PHY_PLL_IDAC_ADJ_CFG },
> - { 0x06, REG_HDMI_8960_PHY_PLL_I_VI_KVCO_CFG },
> - { 0x0a, REG_HDMI_8960_PHY_PLL_PWRDN_B },
> - { 0x7b, REG_HDMI_8960_PHY_PLL_SDM_CFG0 },
> - { 0x01, REG_HDMI_8960_PHY_PLL_SDM_CFG1 },
> - { 0x4c, REG_HDMI_8960_PHY_PLL_SDM_CFG2 },
> - { 0xc0, REG_HDMI_8960_PHY_PLL_SDM_CFG3 },
> - { 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG4 },
> - { 0x9a, REG_HDMI_8960_PHY_PLL_SSC_CFG0 },
> - { 0x00, REG_HDMI_8960_PHY_PLL_SSC_CFG1 },
> - { 0x00, REG_HDMI_8960_PHY_PLL_SSC_CFG2 },
> - { 0x00, REG_HDMI_8960_PHY_PLL_SSC_CFG3 },
> - { 0x10, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG0 },
> - { 0x1a, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG1 },
> - { 0x0d, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2 },
> - { 0x2a, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 },
> - { 0x03, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 },
> - { 0x3b, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 },
> - { 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3 },
> - { 0x86, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 },
> - { 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 },
> - { 0x33, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG6 },
> - { 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG7 },
> - }
> - },
> - /* 640x480p60 */
> - { 25200000, 27, {
> - { 0x32, REG_HDMI_8960_PHY_PLL_REFCLK_CFG },
> - { 0x02, REG_HDMI_8960_PHY_PLL_CHRG_PUMP_CFG },
> - { 0x01, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 },
> - { 0x33, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 },
> - { 0x2c, REG_HDMI_8960_PHY_PLL_IDAC_ADJ_CFG },
> - { 0x06, REG_HDMI_8960_PHY_PLL_I_VI_KVCO_CFG },
> - { 0x0a, REG_HDMI_8960_PHY_PLL_PWRDN_B },
> - { 0x77, REG_HDMI_8960_PHY_PLL_SDM_CFG0 },
> - { 0x4c, REG_HDMI_8960_PHY_PLL_SDM_CFG1 },
> - { 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG2 },
> - { 0xc0, REG_HDMI_8960_PHY_PLL_SDM_CFG3 },
> - { 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG4 },
> - { 0x9a, REG_HDMI_8960_PHY_PLL_SSC_CFG0 },
> - { 0x00, REG_HDMI_8960_PHY_PLL_SSC_CFG1 },
> - { 0x00, REG_HDMI_8960_PHY_PLL_SSC_CFG2 },
> - { 0x20, REG_HDMI_8960_PHY_PLL_SSC_CFG3 },
> - { 0x10, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG0 },
> - { 0x1a, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG1 },
> - { 0x0d, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2 },
> - { 0xf4, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 },
> - { 0x02, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 },
> - { 0x3b, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 },
> - { 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3 },
> - { 0x86, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 },
> - { 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 },
> - { 0x33, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG6 },
> - { 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG7 },
> - }
> - },
> -};
> -
> -static const struct pll_rate *qcom_hdmi_8960_pll_find_rate(unsigned long rate)
> +static inline void write16(u16 val, void __iomem *reg)

No 'inline' keyword in .c files please.

- Mani

--
மணிவண்ணன் சதாசிவம்