Re: [PATCH v2 6/9] clk: renesas: rzg2l: Add support for RZ/G3L DSI mux

[Geert Uytterhoeven]

On Tue, 11 Aug 2026 at 20:27, Biju <biju.das.au@xxxxxxxxx> wrote:
> From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
>
> Add support for RZ/G3L DSI mux that supports 2 duty cycles.
>
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> ---
> v1->v2:
>  * Dropped rzg3l_cpg_dsi_smux_get_duty_cycle().
>  * Updated Mux flags with CLK_DUTY_CYCLE_PARENT and
>    CLK_SET_RATE_NO_REPARENT
>  * Determine rate now forward to clk_mux_ops.determine_rate().
>  * Dropped the duty cycle macros.
>  * Dropped struct rzg3l_dsi_mux_clk and to_plldsi_clk_mux.

Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
i.e. will queue in renesas-clk for v7.4.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

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                                -- Linus Torvalds