Re: [PATCH net v2] net: pcs: enable autonegotiation for 10g-usxgmii

[Patryk Biel]

On Thu, Aug 27, 2026 at 11:48 AM Vladimir Oltean
<vladimir.oltean@xxxxxxx> wrote:
> > Looking at the lynx_pcs_link_up_sgmii, once the neg_mode
> > differs from PHYLINK_PCS_NEG_INBAND_ENABLED, the IF_MODE register is
> > explicitly programmed with speed and duplex values. I browsed through
> > the manual but did not find any similar register for 10g-qxgmii. This
> > may just be due to my limited understanding of this area, but is this
> > intentional? There is no need to epicly program speed and mode for 10g
> > qxmgii with in-band autoneg off?
>
> Yes, I suppose there should be.
>
> I also don't see a register in the MDIO address space.
>
> I do see QXGMIIaCR2 field USX_FORCE_SPD, but that's in the SerDes
> protocol converter wrapper space (which is handled by
> drivers/phy/freescale/phy-fsl-lynx-10g.c), so that's a bit unfortunate.
>
> Looking at this register, it's not clear to me how individual 10G-QXGMII
> ports could have their speeds forced individually to different values.
> The single register handles the entire multi-port protocol converter,
> it's not like QXGMIIaCR4-QXGMIIaCR7 which are per port.
> This is something else I'll have to ask internally.

This is exactly where I ended up with my research as well, and I had
similar thoughts. I would be grateful if you could let me know if you
find out anything more about this.

> > Given all of the above, I just wanted to add that I'll be on vacation
> > for three weeks starting at the beginning of September.
> > So if you'd prefer to send these changes yourself before then, please
> > don't let me be a blocker.
>
> That's fine, I'll also have some vacation time during the same interval,
> you can submit the work to net-next when you return.

Okay, great. I'll prepare v3 then and submit it once net-next reopens
after the merge window.

Best regards
Patryk