[PATCH 2/5] dt-bindings: media: qcom,maili-iris: Add maili video codec binding
From: Wangao Wang
Date: Mon Sep 14 2026 - 09:34:20 EST
Add a devicetree binding for the Iris4 video encoder and decoder block
found on the Qualcomm Maili SoC.
Compared to the Iris3 generation, this block has
- separate power domains for stream and pixel processing hardware blocks
(bse and vpp).
- different clocks and reset lines.
Signed-off-by: Wangao Wang <wangao.wang@xxxxxxxxxxxxxxxx>
---
.../devicetree/bindings/media/qcom,maili-iris.yaml | 235 +++++++++++++++++++++
1 file changed, 235 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/qcom,maili-iris.yaml b/Documentation/devicetree/bindings/media/qcom,maili-iris.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..58d241999824f3cdc85a1d644200be1e4916e324
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/qcom,maili-iris.yaml
@@ -0,0 +1,235 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/qcom,maili-iris.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Maili SoC Iris video encoder and decoder
+
+maintainers:
+ - Vikash Garodia <vikash.garodia@xxxxxxxxxxxxxxxx>
+ - Dikshita Agarwal <dikshita.agarwal@xxxxxxxxxxxxxxxx>
+
+description:
+ The Iris video processing unit on Qualcomm Maili SoC is a video encode and
+ decode accelerator.
+
+properties:
+ compatible:
+ enum:
+ - qcom,maili-iris
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 8
+
+ clock-names:
+ items:
+ - const: iface
+ - const: core
+ - const: vcodec0_core
+ - const: iface1
+ - const: core_freerun
+ - const: vcodec0_core_freerun
+ - const: vcodec_bse
+ - const: vcodec_vpp0
+
+ firmware-name:
+ maxItems: 1
+
+ interconnects:
+ maxItems: 2
+
+ interconnect-names:
+ items:
+ - const: cpu-cfg
+ - const: video-mem
+
+ power-domains:
+ maxItems: 5
+
+ power-domain-names:
+ items:
+ - const: venus
+ - const: vcodec0
+ - const: mxc
+ - const: mmcx
+ - const: vpp0
+
+ resets:
+ maxItems: 4
+
+ reset-names:
+ items:
+ - const: bus0
+ - const: bus1
+ - const: core
+ - const: vcodec0_core
+
+ iommus:
+ maxItems: 4
+
+ dma-coherent: true
+
+ memory-region:
+ minItems: 1
+ items:
+ - description: Firmware-loaded codec carveout
+ - description: IOMMU IOVA reservation region
+
+ operating-points-v2: true
+
+ opp-table:
+ type: object
+
+required:
+ - compatible
+ - dma-coherent
+ - interconnects
+ - interconnect-names
+ - power-domain-names
+ - resets
+ - reset-names
+
+allOf:
+ - $ref: qcom,venus-common.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,hawi-gcc.h>
+ #include <dt-bindings/clock/qcom,maili-videocc.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interconnect/qcom,icc.h>
+ #include <dt-bindings/interconnect/qcom,maili-rpmh.h>
+ #include <dt-bindings/power/qcom,rpmhpd.h>
+
+ video-codec@2000000 {
+ compatible = "qcom,maili-iris";
+ reg = <0x02000000 0xf0000>;
+
+ interrupts = <GIC_ESPI 238 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
+ <&videocc VIDEO_CC_MVS0C_CLK>,
+ <&videocc VIDEO_CC_MVS0_CLK>,
+ <&gcc GCC_VIDEO_AXI0C_CLK>,
+ <&videocc VIDEO_CC_MVS0C_FREERUN_CLK>,
+ <&videocc VIDEO_CC_MVS0_FREERUN_CLK>,
+ <&videocc VIDEO_CC_MVS0B_CLK>,
+ <&videocc VIDEO_CC_MVS0_VPP0_CLK>;
+ clock-names = "iface",
+ "core",
+ "vcodec0_core",
+ "iface1",
+ "core_freerun",
+ "vcodec0_core_freerun",
+ "vcodec_bse",
+ "vcodec_vpp0";
+
+ dma-coherent;
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_IRIS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc MASTER_VIDEO_MVP QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "cpu-cfg",
+ "video-mem";
+
+ memory-region = <&video_mem>;
+
+ power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>,
+ <&videocc VIDEO_CC_MVS0_GDSC>,
+ <&rpmhpd RPMHPD_MXC>,
+ <&rpmhpd RPMHPD_MMCX>,
+ <&videocc VIDEO_CC_MVS0_VPP0_GDSC>;
+ power-domain-names = "venus",
+ "vcodec0",
+ "mxc",
+ "mmcx",
+ "vpp0";
+
+ resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
+ <&gcc GCC_VIDEO_AXI0C_CLK_ARES>,
+ <&videocc VIDEO_CC_MVS0C_FREERUN_CLK_ARES>,
+ <&videocc VIDEO_CC_MVS0_FREERUN_CLK_ARES>;
+ reset-names = "bus0",
+ "bus1",
+ "core",
+ "vcodec0_core";
+
+ operating-points-v2 = <&iris_opp_table>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ dma-ranges = <0x0 0x0 0xffc00000>;
+
+ non-pixel {
+ iommus = <&apps_smmu 0x1540 0x0000>,
+ <&apps_smmu 0x1620 0x0000>,
+ <&apps_smmu 0x1544 0x0000>;
+ iommu-ranges = <0x25800000 0xda400000>;
+ };
+
+ pixel {
+ iommus = <&apps_smmu 0x1543 0x0000>;
+ };
+
+ iris_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-240000000 {
+ opp-hz = /bits/ 64 <240000000 240000000 360000000>;
+ required-opps = <&rpmhpd_opp_low_svs_d2>,
+ <&rpmhpd_opp_low_svs_d1>;
+ };
+
+ opp-338000000 {
+ opp-hz = /bits/ 64 <338000000 338000000 507000000>;
+ required-opps = <&rpmhpd_opp_low_svs_d1>,
+ <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-420000000 {
+ opp-hz = /bits/ 64 <420000000 420000000 630000000>;
+ required-opps = <&rpmhpd_opp_svs>,
+ <&rpmhpd_opp_svs>;
+ };
+
+ opp-444000000 {
+ opp-hz = /bits/ 64 <444000000 444000000 666000000>;
+ required-opps = <&rpmhpd_opp_svs>,
+ <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000 533000000 800000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>,
+ <&rpmhpd_opp_nom>;
+ };
+
+ opp-630000000 {
+ opp-hz = /bits/ 64 <630000000 630000000 1104000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>,
+ <&rpmhpd_opp_turbo>;
+ };
+
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000 630000000 1260000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>,
+ <&rpmhpd_opp_turbo_l1>;
+ };
+
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000 800000000 1260000000>;
+ required-opps = <&rpmhpd_opp_nom>,
+ <&rpmhpd_opp_turbo_l3>;
+ };
+ };
+ };
--
2.43.0