Re: [PATCH RESEND v4 1/3] perf/amd/ibs: Limit the max EILVT register count for AMD family 0x10

[Borislav Petkov]

On Thu, Sep 03, 2026 at 02:58:39PM +0530, Naveen N Rao (AMD) wrote:
> For AMD family 0x10, EILVT offsets are not assigned by BIOS and is
> instead assigned by picking the next available EILVT offset.  Use the
> maximum EILVT count for family 0x10 (APIC_EILVT_NR_AMD_10H) rather than
> an arbitrary maximum EILVT count when looking for the next available
> EILVT offset.

Huh?

#define         APIC_EILVT_NR_MAX       APIC_EILVT_NR_AMD_10H

What is this "fixing"?

Also,

+ Robert

who happens to know something about that code. Don't forget to use git
annotate, do some git archeology and CC the relevant people on patches.

Leaving in the rest for him.

> Signed-off-by: Naveen N Rao (AMD) <naveen@xxxxxxxxxx>
> Tested-by: Manali Shukla <manali.shukla@xxxxxxx>
> ---
>  arch/x86/events/amd/ibs.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c
> index 3531f9c23b8c..555912ac520f 100644
> --- a/arch/x86/events/amd/ibs.c
> +++ b/arch/x86/events/amd/ibs.c
> @@ -1839,13 +1839,13 @@ static void force_ibs_eilvt_setup(void)
>  
>  	preempt_disable();
>  	/* find the next free available EILVT entry, skip offset 0 */
> -	for (offset = 1; offset < APIC_EILVT_NR_MAX; offset++) {
> +	for (offset = 1; offset < APIC_EILVT_NR_AMD_10H; offset++) {
>  		if (get_eilvt(offset))
>  			break;
>  	}
>  	preempt_enable();
>  
> -	if (offset == APIC_EILVT_NR_MAX) {
> +	if (offset == APIC_EILVT_NR_AMD_10H) {
>  		pr_debug("No EILVT entry available\n");
>  		return;
>  	}
> -- 
> 2.55.0
> 

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette