Re: [PATCH v5 1/3] dt-bindings: edac: cdns,ddr-edac: add Cadence DDR EDAC
From: Rob Herring (Arm)
Date: Tue Oct 06 2026 - 12:00:44 EST
On Mon, 05 Oct 2026 14:49:22 +0200, Paul Louvel wrote:
> Add the Cadence EDAC dt binding.
> The memory controller optionally supports ECC SECDED with DDR2/DDR3
> memory.
>
> Reviewed-by: Wolfram Sang <wsa+renesas@xxxxxxxxxxxxxxxxxxxx>
> Signed-off-by: Paul Louvel (Schneider Electric) <paul.louvel@xxxxxxxxxxx>
> ---
> .../devicetree/bindings/edac/cdns,ddr-edac.yaml | 61 ++++++++++++++++++++++
> MAINTAINERS | 6 +++
> 2 files changed, 67 insertions(+)
>
Reviewed-by: Rob Herring (Arm) <robh@xxxxxxxxxx>