Re: [PATCH v5 1/3] dt-bindings: edac: cdns,ddr-edac: add Cadence DDR EDAC

[Paul Louvel]

On Mon Oct 5, 2026 at 8:46 PM CEST, Borislav Petkov wrote:
> On Mon, Oct 05, 2026 at 02:49:22PM +0200, Paul Louvel wrote:
>> Add the Cadence EDAC dt binding.
>> The memory controller optionally supports ECC SECDED with DDR2/DDR3
>> memory.
>> 
>> Reviewed-by: Wolfram Sang <wsa+renesas@xxxxxxxxxxxxxxxxxxxx>
>> Signed-off-by: Paul Louvel (Schneider Electric) <paul.louvel@xxxxxxxxxxx>
>> ---
>>  .../devicetree/bindings/edac/cdns,ddr-edac.yaml    | 61 ++++++++++++++++++++++
>>  MAINTAINERS                                        |  6 +++
>>  2 files changed, 67 insertions(+)
>
> Needs review by DT maintainers if it is going to go through the EDAC tree, see
> output of:
>
> ./scripts/get_maintainer.pl -f Documentation/devicetree/bindings/edac/

ACK.
For some reason b4 did not included most of the people apart from Rob /
Krzysztof / Wolfram.

-- 
Paul Louvel, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com