[PATCH 19/45] media: qcom: camss: sm8250: add pixel path resources

From: Gjorgji . Rosikopulos . gjorgji . rosikopulos

Date: Tue Oct 06 2026 - 18:52:54 EST

From: Atanas Filipov <atanas.filipov@xxxxxxxxxxxxxxxx>

Add CSID, IFE, and IFE Lite resources for the SM8250 pixel path. Select
them with the qcom,sm8250pix-camss compatible.

Signed-off-by: Atanas Filipov <atanas.filipov@xxxxxxxxxxxxxxxx>
---
drivers/media/platform/qcom/camss/camss.c | 224 +++++++++++++++++++++-
1 file changed, 222 insertions(+), 2 deletions(-)

diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index 7c355003c957..2dc7864ebe07 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -27,6 +27,7 @@
#include <media/v4l2-mc.h>
#include <media/v4l2-fwnode.h>

+#include "camss-ife-camif-v10x.h"
#include "camss.h"

#define CAMSS_CLOCK_MARGIN_NUMERATOR 105
@@ -36,6 +37,7 @@
#define CAMSS_NUM_OF_PIXELS_PER_CYCLE 2

static const struct parent_dev_ops vfe_parent_dev_ops;
+static const struct parent_dev_ops ife_parent_dev_ops;

static const struct camss_subdev_resources csiphy_res_8x16[] = {
/* CSIPHY0 */
@@ -2269,6 +2271,208 @@ static const struct resources_icc icc_res_sm8250[] = {
},
};

+static const struct camss_ife_stream csid_ife_streams_sm8250pix[] = {
+ { .id = 0, .pipe = CAMSS_IFE_HW_PIPE_RDI0 },
+ { .id = 1, .pipe = CAMSS_IFE_HW_PIPE_RDI1 },
+ { .id = 2, .pipe = CAMSS_IFE_HW_PIPE_RDI2 },
+ { .id = 3, .pipe = CAMSS_IFE_HW_PIPE_PP },
+};
+
+static const struct camss_ife_stream csid_ife_lite_streams_sm8250pix[] = {
+ { .id = 0, .pipe = CAMSS_IFE_HW_PIPE_RDI0 },
+ { .id = 1, .pipe = CAMSS_IFE_HW_PIPE_RDI1 },
+ { .id = 2, .pipe = CAMSS_IFE_HW_PIPE_RDI2 },
+ { .id = 3, .pipe = CAMSS_IFE_HW_PIPE_RDI3 },
+};
+
+static const struct camss_subdev_resources csid_res_sm8250pix[] = {
+ /* CSID0 */
+ {
+ .regulators = {},
+ .clock = { "vfe0_csid", "vfe0_cphy_rx", "vfe0", "vfe0_areg", "vfe0_ahb" },
+ .clock_rate = { { 400000000 },
+ { 400000000 },
+ { 350000000, 475000000, 576000000, 720000000 },
+ { 100000000, 200000000, 300000000, 400000000 },
+ { 0 } },
+ .reg = { "csid0" },
+ .interrupt = { "csid0" },
+ .csid = {
+ .streams_enable = true,
+ .source_streams_mode = CSID_STREAMS_SINGLE_PAD,
+ .hw_ops = &csid_ops_gen2,
+ .parent_dev_ops = &ife_parent_dev_ops,
+ .formats = &csid_formats_gen2,
+ }
+ },
+ /* CSID1 */
+ {
+ .regulators = {},
+ .clock = { "vfe1_csid", "vfe1_cphy_rx", "vfe1", "vfe1_areg", "vfe1_ahb" },
+ .clock_rate = { { 400000000 },
+ { 400000000 },
+ { 350000000, 475000000, 576000000, 720000000 },
+ { 100000000, 200000000, 300000000, 400000000 },
+ { 0 } },
+ .reg = { "csid1" },
+ .interrupt = { "csid1" },
+ .csid = {
+ .streams_enable = true,
+ .source_streams_mode = CSID_STREAMS_SINGLE_PAD,
+ .hw_ops = &csid_ops_gen2,
+ .parent_dev_ops = &ife_parent_dev_ops,
+ .formats = &csid_formats_gen2,
+ }
+ },
+ /* CSID2 */
+ {
+ .regulators = {},
+ .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx", "vfe_lite", "vfe_lite_ahb" },
+ .clock_rate = { { 400000000 },
+ { 400000000 },
+ { 400000000, 480000000 },
+ { 0 } },
+ .reg = { "csid2" },
+ .interrupt = { "csid2" },
+ .csid = {
+ .is_lite = true,
+ .streams_enable = true,
+ .hw_ops = &csid_ops_gen2,
+ .parent_dev_ops = &ife_parent_dev_ops,
+ .formats = &csid_formats_gen2,
+ }
+ },
+ /* CSID3 */
+ {
+ .regulators = {},
+ .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx", "vfe_lite", "vfe_lite_ahb" },
+ .clock_rate = { { 400000000 },
+ { 400000000 },
+ { 400000000, 480000000 },
+ { 0 } },
+ .reg = { "csid3" },
+ .interrupt = { "csid3" },
+ .csid = {
+ .is_lite = true,
+ .streams_enable = true,
+ .hw_ops = &csid_ops_gen2,
+ .parent_dev_ops = &ife_parent_dev_ops,
+ .formats = &csid_formats_gen2,
+ }
+ }
+};
+
+static const struct camss_subdev_resources ife_res_sm8250pix[] = {
+ /* IFE0 */
+ {
+ .regulators = {},
+ .clock = { "camnoc_axi_src", "slow_ahb_src", "cpas_ahb",
+ "camnoc_axi", "vfe0_ahb", "vfe0_areg", "vfe0",
+ "vfe0_axi", "cam_hf_axi" },
+ .clock_rate = { { },
+ { },
+ { },
+ { },
+ { },
+ { 19200000, 100000000, 200000000, 300000000, 400000000 },
+ { 19200000, 350000000, 475000000, 576000000, 680000000 },
+ { 19200000, 300000000, 400000000, 400000000, 400000000 },
+ { } },
+ .reg = { "vfe0" },
+ .interrupt = { "vfe0" },
+ .ife = {
+ .type = CAMSS_IFE_SUBDEV_TYPE_IFE,
+ .pads = &ife_pads_v20x,
+ .top_ops = &ife_top_20x_ops,
+ .camif_ops = &ife_camif_v10x_ops,
+ .mod_ops = &ife_mod_v10x_ops,
+ .buswr_ops = &ife_buswr_20x_ops,
+ .num_sink_streams = ARRAY_SIZE(csid_ife_streams_sm8250pix),
+ .sink_streams = csid_ife_streams_sm8250pix,
+ },
+ },
+ /* IFE1 */
+ {
+ .regulators = {},
+ .clock = { "camnoc_axi_src", "slow_ahb_src", "cpas_ahb",
+ "camnoc_axi", "vfe1_ahb", "vfe1_areg", "vfe1",
+ "vfe1_axi", "cam_hf_axi" },
+ .clock_rate = { { },
+ { },
+ { },
+ { },
+ { },
+ { 19200000, 100000000, 200000000, 300000000, 400000000 },
+ { 19200000, 350000000, 475000000, 576000000, 680000000 },
+ { 19200000, 300000000, 400000000, 400000000, 400000000 },
+ { } },
+ .reg = { "vfe1" },
+ .interrupt = { "vfe1" },
+ .ife = {
+ .type = CAMSS_IFE_SUBDEV_TYPE_IFE,
+ .pads = &ife_pads_v20x,
+ .top_ops = &ife_top_20x_ops,
+ .camif_ops = &ife_camif_v10x_ops,
+ .mod_ops = &ife_mod_v10x_ops,
+ .buswr_ops = &ife_buswr_20x_ops,
+ .num_sink_streams = ARRAY_SIZE(csid_ife_streams_sm8250pix),
+ .sink_streams = csid_ife_streams_sm8250pix,
+ },
+ },
+ /* IFE2 (lite) */
+ {
+ .regulators = {},
+ .clock = { "camnoc_axi_src", "slow_ahb_src", "cpas_ahb",
+ "camnoc_axi", "vfe_lite_ahb", "vfe_lite_axi",
+ "vfe_lite", "cam_hf_axi" },
+ .clock_rate = { { },
+ { },
+ { },
+ { },
+ { },
+ { 19200000, 300000000, 400000000, 400000000, 400000000 },
+ { 19200000, 400000000, 480000000, 480000000, 480000000 },
+ { } },
+ .reg = { "vfe_lite0" },
+ .interrupt = { "vfe_lite0" },
+ .ife = {
+ .type = CAMSS_IFE_SUBDEV_TYPE_IFE_LITE,
+ .pads = &ife_lite_pads_v20x,
+ .top_ops = &ife_lite_top_10x_ops,
+ .camif_ops = &ife_camif_v10x_ops,
+ .buswr_ops = &ife_buswr_20x_ops,
+ .num_sink_streams = ARRAY_SIZE(csid_ife_lite_streams_sm8250pix),
+ .sink_streams = csid_ife_lite_streams_sm8250pix,
+ }
+ },
+ /* IFE3 (lite) */
+ {
+ .regulators = {},
+ .clock = { "camnoc_axi_src", "slow_ahb_src", "cpas_ahb",
+ "camnoc_axi", "vfe_lite_ahb", "vfe_lite_axi",
+ "vfe_lite", "cam_hf_axi" },
+ .clock_rate = { { },
+ { },
+ { },
+ { },
+ { },
+ { 19200000, 300000000, 400000000, 400000000, 400000000 },
+ { 19200000, 400000000, 480000000, 480000000, 480000000 },
+ { } },
+ .reg = { "vfe_lite1" },
+ .interrupt = { "vfe_lite1" },
+ .ife = {
+ .type = CAMSS_IFE_SUBDEV_TYPE_IFE_LITE,
+ .pads = &ife_lite_pads_v20x,
+ .top_ops = &ife_lite_top_10x_ops,
+ .camif_ops = &ife_camif_v10x_ops,
+ .buswr_ops = &ife_buswr_20x_ops,
+ .num_sink_streams = ARRAY_SIZE(csid_ife_lite_streams_sm8250pix),
+ .sink_streams = csid_ife_lite_streams_sm8250pix,
+ }
+ },
+};
+
static const struct camss_subdev_resources csiphy_res_7280[] = {
/* CSIPHY0 */
{
@@ -4977,10 +5181,10 @@ static void __iomem
return NULL;
}

-static const struct parent_dev_ops ife_parent_dev_ops __maybe_unused = {
+static const struct parent_dev_ops ife_parent_dev_ops = {
.get = ife_parent_dev_ops_get,
.put = ife_parent_dev_ops_put,
- .get_base_address = ife_parent_dev_ops_get_base_address
+ .get_base_address = ife_parent_dev_ops_get_base_address,
};

int camss_attach_host_data(struct camss *camss, struct v4l2_subdev *sd,
@@ -6142,6 +6346,21 @@ static const struct camss_resources sm8250_resources = {
.csid_vfe_fixed_pairing = true,
};

+static const struct camss_resources sm8250pix_resources = {
+ .version = CAMSS_8250,
+ .csiphy_res = csiphy_res_8250,
+ .csid_res = csid_res_sm8250pix,
+ .ife_res = ife_res_sm8250pix,
+ .icc_res = icc_res_sm8250,
+ .icc_path_num = ARRAY_SIZE(icc_res_sm8250),
+ .csiphy_num = ARRAY_SIZE(csiphy_res_8250),
+ .csid_num = ARRAY_SIZE(csid_res_sm8250pix),
+ .embedded_csid = true,
+ .ife_num = 2,
+ .ife_lite_num = 2,
+ .link_entities = camss_ife_link_entities,
+};
+
static const struct camss_resources sc8280xp_resources = {
.version = CAMSS_8280XP,
.pd_name = "top",
@@ -6229,6 +6448,7 @@ static const struct of_device_id camss_dt_match[] = {
{ .compatible = "qcom,sm6150-camss", .data = &sm6150_resources },
{ .compatible = "qcom,sm6350-camss", .data = &sm6350_resources },
{ .compatible = "qcom,sm8250-camss", .data = &sm8250_resources },
+ { .compatible = "qcom,sm8250pix-camss", .data = &sm8250pix_resources },
{ .compatible = "qcom,sm8550-camss", .data = &sm8550_resources },
{ .compatible = "qcom,sm8650-camss", .data = &sm8650_resources },
{ .compatible = "qcom,x1e80100-camss", .data = &x1e80100_resources },
--
2.34.1