[PATCH 45/45] media: qcom: camss: sa8775p: add pixel path resources for QCS8300
From: Gjorgji . Rosikopulos . gjorgji . rosikopulos
Date: Tue Oct 06 2026 - 18:52:58 EST
From: Prashant Shrotriya <prashant.shrotriya@xxxxxxxxxxxxxxxx>
QCS8300 shares the same IFE/CSID pixel path hardware as SA8775P, with
one difference: QCS8300 has 3 CSIPHYs (0-2) while SA8775P has 4
(0-3).
Add csiphy_res_qcs8300_pix with streams_enable set on each entry, as
required by the CSID pixel path driver, and a qcs8300_pix_resources
table that reuses the SA8775P CSID/IFE/TPG resources together with
the QCS8300 ICC bandwidth paths.
Signed-off-by: Prashant Shrotriya <prashant.shrotriya@xxxxxxxxxxxxxxxx>
---
drivers/media/platform/qcom/camss/camss.c | 84 +++++++++++++++++++++++
1 file changed, 84 insertions(+)
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index a0b51c12c0bf..4233357321c0 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -4469,6 +4469,72 @@ static const struct camss_subdev_resources csiphy_res_sa8775p_pix[] = {
},
};
+static const struct camss_subdev_resources csiphy_res_qcs8300_pix[] = {
+ /* CSIPHY0 */
+ {
+ .regulators = {
+ { .supply = "vdda-phy", .init_load_uA = 15900 },
+ { .supply = "vdda-pll", .init_load_uA = 8900 }
+ },
+ .clock = { "csiphy_rx", "csiphy0", "csiphy0_timer" },
+ .clock_rate = {
+ { 400000000 },
+ { 0 },
+ { 400000000 },
+ },
+ .reg = { "csiphy0" },
+ .interrupt = { "csiphy0" },
+ .csiphy = {
+ .id = 0,
+ .streams_enable = true,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845
+ }
+ },
+ /* CSIPHY1 */
+ {
+ .regulators = {
+ { .supply = "vdda-phy", .init_load_uA = 15900 },
+ { .supply = "vdda-pll", .init_load_uA = 8900 }
+ },
+ .clock = { "csiphy_rx", "csiphy1", "csiphy1_timer" },
+ .clock_rate = {
+ { 400000000 },
+ { 0 },
+ { 400000000 },
+ },
+ .reg = { "csiphy1" },
+ .interrupt = { "csiphy1" },
+ .csiphy = {
+ .id = 1,
+ .streams_enable = true,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845
+ }
+ },
+ /* CSIPHY2 */
+ {
+ .regulators = {
+ { .supply = "vdda-phy", .init_load_uA = 15900 },
+ { .supply = "vdda-pll", .init_load_uA = 8900 }
+ },
+ .clock = { "csiphy_rx", "csiphy2", "csiphy2_timer" },
+ .clock_rate = {
+ { 400000000 },
+ { 0 },
+ { 400000000 },
+ },
+ .reg = { "csiphy2" },
+ .interrupt = { "csiphy2" },
+ .csiphy = {
+ .id = 2,
+ .streams_enable = true,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845
+ }
+ },
+};
+
static const struct camss_ife_stream csid_ife_streams_sa8775p_pix[] = {
{ .id = 0, .pipe = CAMSS_IFE_HW_PIPE_RDI0 },
{ .id = 1, .pipe = CAMSS_IFE_HW_PIPE_RDI1 },
@@ -6698,6 +6764,23 @@ static const struct camss_resources sa8775p_pix_resources = {
.link_entities = camss_ife_link_entities
};
+static const struct camss_resources qcs8300_pix_resources = {
+ .version = CAMSS_8300,
+ .csiphy_res = csiphy_res_qcs8300_pix,
+ .tpg_res = tpg_res_8775p,
+ .csid_res = csid_res_sa8775p_pix,
+ .csid_wrapper_res = &csid_wrapper_res_sm8550,
+ .ife_res = ife_res_sa8775p_pix,
+ .icc_res = icc_res_qcs8300,
+ .icc_path_num = ARRAY_SIZE(icc_res_qcs8300),
+ .csiphy_num = ARRAY_SIZE(csiphy_res_qcs8300_pix),
+ .tpg_num = ARRAY_SIZE(tpg_res_8775p),
+ .csid_num = ARRAY_SIZE(csid_res_sa8775p_pix),
+ .ife_num = 2,
+ .ife_lite_num = 5,
+ .link_entities = camss_ife_link_entities
+};
+
static const struct camss_resources sdm660_resources = {
.version = CAMSS_660,
.csiphy_res = csiphy_res_660,
@@ -6873,6 +6956,7 @@ static const struct of_device_id camss_dt_match[] = {
{ .compatible = "qcom,sm6350-camss", .data = &sm6350_resources },
{ .compatible = "qcom,sm8250-camss", .data = &sm8250_resources },
{ .compatible = "qcom,sa8775p-camss-pix", .data = &sa8775p_pix_resources },
+ { .compatible = "qcom,qcs8300-camss-pix", .data = &qcs8300_pix_resources },
{ .compatible = "qcom,sm8250pix-camss", .data = &sm8250pix_resources },
{ .compatible = "qcom,sm8550-camss", .data = &sm8550_resources },
{ .compatible = "qcom,sm8650-camss", .data = &sm8650_resources },
--
2.34.1