Re: [PATCH net-next v13 02/12] dt-bindings: dpll: add SiTime SiT95316 clock generator

[Ali Rouhi]

On Wed, 14 Oct 2026, sashiko-bot@xxxxxxxxxx wrote:

Reply inline.

> [Severity: Low] The description states this must be a single entry,
> but should there be a maxItems: 1 constraint to structurally enforce
> this? Without it, a device tree node providing an array of multiple
> 64-bit frequencies for an input pin will silently pass schema
> validation.

Agreed, and v14 adds it.

The example was the problem, not the schema.  The rates were written
/bits/ 64, and supported-frequencies-hz is a 32-bit type, so each rate
decoded as two cells and maxItems: 1 failed on the example itself:

  input-pins:pin@0:supported-frequencies-hz: [[0], [10000000]] is too long

Rob Herring asked for the 32-bit width on this patch independently.
With the examples corrected the constraint holds, and it is in v14 on
the input pin list.  The output pins keep an unbounded list, since an
output can be set to any of several rates.