Re: [PATCH net-next v13 08/12] dpll: sit9531x: add support to get and set frequency on pins

[Ali Rouhi]

On Wed, 14 Oct 2026, sashiko-bot@xxxxxxxxxx wrote:

Reply inline.

> [Severity: Medium] Since the device registers are big-endian, does
> this loop reverse the byte order? By looping i from 3 down to 0 and
> shifting the result left, the value from the highest address (which
> should be the LSB) is placed into the most significant byte of
> fracn_raw, which could result in incorrect VCO frequency
> calculations.

The loop matches the register layout, which is the other way around.
The numerator's least significant byte sits at the lowest of its four
addresses and its most significant byte at the highest, so reading the
highest address first and shifting left each time reconstructs the
value.

> [Severity: Medium] Similarly for the denominator, is the byte order
> also reversed here by reading the highest address first and shifting
> it into the MSB?

The denominator has the same layout and the same loop.