[PATCH 0/9] Fix USB2 and USB3 on NSP SoCs

[Florian Fainelli]

Similar to the SATA patch series, USB2 and USB3 on Northstar Plus SoCs
was broken in a few different areas:

- the NSP variant was not described properly at the USB PHY level which
  prevented SoC-specific initialization from occurring
- the lack of DMP registers meant that the USB PHY could not complete
  the initilization and instead relies on the boot loader
- the EHCI controller requires some FIFO tuning which is similar to the
  XGS iProc SoC, otherwise DMA transfers eventually fail
- finally, the USB controllers are non coherent

Florian Fainelli (9):
  phy: broadcom: ns-usb3: Propagate Bx initialization write errors
  dt-bindings: phy: bcm-ns-usb3-phy: Describe the NSP variant
  phy: broadcom: ns-usb3: Coordinate NSP USB2 and USB3 initialization
  ARM: dts: broadcom: Add the NSP USB2 DMP registers
  ARM: dts: broadcom: Share USB PHY initialization on BCM958625HR
  dt-bindings: usb: generic-ehci: Add the NSP compatible
  usb: host: ehci-platform: Set the FIFO threshold on NSP
  ARM: dts: broadcom: Identify the NSP EHCI controller
  ARM: dts: broadcom: Use noncoherent USB DMA on BCM958625HR

 .../bindings/phy/bcm-ns-usb3-phy.yaml         |  23 +++
 .../devicetree/bindings/usb/generic-ehci.yaml |   1 +
 arch/arm/boot/dts/broadcom/bcm-nsp.dtsi       |   6 +-
 arch/arm/boot/dts/broadcom/bcm958625hr.dts    |   9 ++
 drivers/phy/broadcom/phy-bcm-ns-usb3.c        | 134 +++++++++++++-----
 drivers/usb/host/ehci-platform.c              |   3 +-
 6 files changed, 139 insertions(+), 37 deletions(-)

-- 
2.53.0