Re: [PATCH] clk: qcom: gcc-ipq6018: add fallback names for the bias PLL parents

[Konrad Dybcio]

On 10/23/26 11:41 AM, Robert Marko wrote:
> On Wed, Oct 21, 2026 at 10:06 AM Konrad Dybcio
> <konrad.dybcio@xxxxxxxxxxxxxxxx> wrote:
>>
>> On 10/20/26 1:39 PM, Robert Marko wrote:
>>>
>>> On 20/10/2026 08:54, Julius Bairaktaris wrote:
>>>> From: Vladyslav Andreichykov <vladdrako007@xxxxxxxxx>
>>>>
>>>> bias_pll_cc_clk and bias_pll_nss_noc_clk are outputs of the CMN PLL,
>>>> which takes its AHB and SYS clocks from GCC, so the device tree does not
>>>> pass them back to GCC. With only .fw_name these parents never resolve,
>>>> nss_ppe_clk_src stays an orphan, and setting it to 300 MHz fails with
>>>> -EINVAL. The NSS clocks below it, such as gcc_nss_edma_clk, read 0 Hz.
>>>>
>>>> Add .name fallbacks so they resolve to the clocks the CMN PLL registers,
>>>> as gcc-ipq8074 already does.
>>>>
>>>> Tested-by: Vladyslav Andreichykov <vladdrako007@xxxxxxxxx>
>>>> Assisted-by: Claude:claude-opus-5-5
>>>> Signed-off-by: Vladyslav Andreichykov <vladdrako007@xxxxxxxxx>
>>>> Signed-off-by: Julius Bairaktaris <julius@xxxxxxxxxxxxxx>
>>>> ---
>>>
>>> Hi,
>>>
>>> This issue does not exist upstream, as CMN PLL is not yet wired due to missing
>>> networking, even then the solution is not to add global name matching.
>>>
>>> The required clock inputs should just be passed to GCC directly which I have
>>> just pushed to OpenWrt.
>>
>> Just read your reply after writing mine, I'm looking forward to seeing
>> that patch!
> 
> Hi Konrad,
> You mean the wiring for CMN PLL or?

Yes the wiring 

Konrad