Re: [PATCH v2 12/12] arm64: dts: qcom: qcs615: Add GP M/N clock controller

[Abel Vesa]

On 26-10-26 16:59:38, Taniya Das wrote:
> Add the GP M/N clock controller and its pin configuration for QCS615.
> The controller uses the PDM XO4 and AHB clocks from GCC and routes its
> output to gpio29.
> 
> Signed-off-by: Taniya Das <taniya.das@xxxxxxxxxxxxxxxx>
> ---
>  arch/arm64/boot/dts/qcom/talos.dtsi | 21 +++++++++++++++++++++
>  1 file changed, 21 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi
> index 8ed6f2755705c38796698747dfe7bba1afd1859e..c415e782804ca8c9d09670cb8c8cd2353d796b23 100644
> --- a/arch/arm64/boot/dts/qcom/talos.dtsi
> +++ b/arch/arm64/boot/dts/qcom/talos.dtsi
> @@ -1611,6 +1611,13 @@ cam_mclk1_default: cam-mclk1-default-state {
>  				bias-disable;
>  			};
>  
> +			gp_mn_active: gp-mn-active-state {
> +				pins = "gpio29";
> +				function = "gp_mn";
> +				drive-strength = <2>;
> +				bias-disable;
> +			};
> +
>  			cam_mclk2_default: cam-mclk2-default-state {
>  				pins = "gpio30";
>  				function = "cam_mclk";
> @@ -4028,6 +4035,20 @@ opp-202000000 {
>  			};
>  		};
>  
> +		gp_mn: clock-controller@88d3000 {
> +			compatible = "qcom,qcs615-gp-mnd", "qcom,sc7280-gp-mnd";
> +			reg = <0x0 0x088d3000 0x0 0x1000>;
> +			clocks = <&gcc GCC_PDM_XO4_CLK>,
> +				 <&gcc GCC_PDM_AHB_CLK>;
> +			clock-names = "pdm_clk", "ahb_clk";
> +			#clock-cells = <0>;
> +			pinctrl-names = "default";
> +			pinctrl-0 = <&gp_mn_active>;

pinctrl-0
pinctrl-names

> +			assigned-clocks = <&gcc GCC_PDM_XO4_CLK>;
> +			assigned-clock-rates = <19200000>;
> +			status = "disabled";
> +		};
> +
>  		qspi: spi@88df000 {
>  			compatible = "qcom,qcs615-qspi",
>  				     "qcom,qspi-v1";
> 
> -- 
> 2.34.1
>