Re: [PATCH v2] MIPS: SGI-IP27: Install the cache error vector on every CPU

[Maciej W. Rozycki]

On Mon, 26 Oct 2026, Imre Kaloz wrote:

> The R10000 drives an uncached attribute on the bus, decoded by the hub.
> CKSEG1 uses attribute 0, UALIAS, whose low 128K is flipped by CPU slice
> (UALIAS_FLIP_BIT), so slice 1 reads CKSEG1 0x100 from node memory
> 0x10100. trap_init() writes the vector only through TO_UNCAC(),
> attribute 3, unflipped. Copy it on each secondary.

 OK, slice 1 gets 0xffffffffa0000100 virtual mapped to 0x10100 physical.

 So does slice 0 get 0xffffffffa0000100 virtual mapped to 0x100 physical?  
How about other slices?  "Each secondary" suggests there are more than 2.

 Not questioning the validity of the change, but trying to understand the 
system topology.

  Maciej