Re: [PATCH v2] MIPS: SGI-IP27: Install the cache error vector on every CPU

[Imre Kaloz]

On Mon, Oct 26, 2026, at 21:15, Maciej W. Rozycki wrote:
> On Mon, 26 Oct 2026, Imre Kaloz wrote:
>
>> The R10000 drives an uncached attribute on the bus, decoded by the hub.
>> CKSEG1 uses attribute 0, UALIAS, whose low 128K is flipped by CPU slice
>> (UALIAS_FLIP_BIT), so slice 1 reads CKSEG1 0x100 from node memory
>> 0x10100. trap_init() writes the vector only through TO_UNCAC(),
>> attribute 3, unflipped. Copy it on each secondary.
>
>  OK, slice 1 gets 0xffffffffa0000100 virtual mapped to 0x10100 physical.
>
>  So does slice 0 get 0xffffffffa0000100 virtual mapped to 0x100 physical?  

Yes, only slice 1 is flipped. UALIAS is node-local, tho: slice 0 on node N
reads node N's 0x100 and slice 1 node N's 0x10100.

> How about other slices?  "Each secondary" suggests there are more than 2.

A hub has two slices, so the flip is the only difference within a node;
"each secondary" means every non-boot CPU across all nodes. trap_init()
writes node 0's 0x100, and per_hub_init() already copies node 0's low
0x200 bytes into every other node, so slice 0 is covered everywhere and
slice 1 on every node was not. Doing the copy on every secondary keeps
it simple; on a slice 0 CPU it rewrites what per_hub_init() put there.


Imre