On Mon, Apr 03, 2000 at 03:35:25PM -0400, Ralph Blach wrote:
> In the IBM 405gp, one can have instruction cache alias. Ie, multiple
> real address in the
> cache in two separate cache lines. This is because the instruction
> cache an way size is
> bigger than page size. In linux, is there ever a time when a real
> instruction page has two differnent virutal address. If so, how does
> this occur?
Yes, you can have the same physical instruction page mapped at different
virtual addresses in different processes. This is quite normal with
shared libraries. You could theoretically also have this if your process
did an mmap itself of the same executable at two addresses; but this
is quite unusual. It doesn't matter though if your instruction caches
contains aliases since you never write to an instruction page.
Data pages are an entirely different problem and aliases do matter.
There are several papers on this; the one I currently have in front
of me is by Wheeler & Bershad at CMU.
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