Instruction Cache Alias and the 405

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In the IBM 405gp, one can have instruction cache alias. Ie, multiple
real address in the
cache in two separate cache lines. This is because the instruction
cache an way size is
bigger than page size. In linux, is there ever a time when a real
instruction page has two differnent virutal address. If so, how does
this occur?

Thanks

Chip Blach
IBM MicroElectronics.

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