But is it possible that I could change the value on 1 Processor and that
doesn't get invalidated in the caches of other Processors -- I think that should
work on the x86, but I completely don't know on other architectures.
-- Linda A Walsh | Trust Technology, Core Linux, SGI law@sgi.com | Voice: (650) 933-5338> -----Original Message----- > From: kaos@kao2.melbourne.sgi.com [mailto:kaos@kao2.melbourne.sgi.com]On > Behalf Of Keith Owens > Sent: Thursday, July 20, 2000 7:37 PM > To: Linda Walsh > Cc: linux-kernel@vger.rutgers.edu > Subject: Re: Cache coherency... and locking > > > On Thu, 20 Jul 2000 18:32:11 -0700, > "Linda Walsh" <law@sgi.com> wrote: > >Suppose I have a variable (a global int) that I'm going to read alot but set > >infrequently. By my understanding, on x86SMP, it uses a Exclusive/Shared/Invalid > >Bus protocol that when one processor changes a cache entry, all the other > >processors are sent invalidates for that cache line. So is it wrong to > >assume that if the only operations are the above, read frequent, and write > >rarely, I don't need locking? > > AFAIK, all the SMP architectures that we care about guarantee that > reads of small, correctly aligned objects are SMP safe. The hardware > ensures that you get consistent bytes, you either see all of the > changes or none of them, you never see a partial update. So if you > change a value from 0x01020304 to 0x05060708 then a concurrent reader > will either see 0x01020304 or 0x05060708, never 0x05060304. > > How small an object has to be to get this guarantee varies from one > arch to another. For example i386 only guarantees 4 byte integrity on > 4 byte boundaries, s390 guarantees 8 byte integrity but only when > aligned on 8 byte boundary, not on 4 byte boundary. > >
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