On Thu, 20 Jul 2000 19:40:34 -0700,
"Linda Walsh" <law@sgi.com> wrote:
>But is it possible that I could change the value on 1 Processor and that
>doesn't get invalidated in the caches of other Processors -- I think that should
>work on the x86, but I completely don't know on other architectures.
Linux SMP assumes cache coherent hardware. From a note by David Miller
to l-k in 1996 and AFAIK never rescinded :-
e) Currently, it is assumed that coherence in a
multiprocessor environment is maintained by the
cache/memory subsystem. That is to say, when
one processor requests a datum on the memory bus
and another processor has a more uptodate copy,
by whatever means the requestor will get the
uptodate copy owned by the other processor.
(NOTE: SMP architectures without hardware cache coherence
mechanisms are indeed possible, the current flush
architecture does not handle this currently. If at
at some point a Linux port to some system where this
is an issue occurrs, I will add the necessary hooks.
But it will not be pretty.)
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