Jeff V. Merkey wrote:
> The best info I know of is to get an analyser that plugs into the
> processor socket (like an american arium) and enable branch trace
> messaging to monitor the interaction between the processor and the cache
> controllers. You get info that's not in any Intel book just watching
> the thing run. Nasty complicated stuff. They explain some of it in the
> cache controller architecture manuals -- these are public.
I still don't see how processor traces will tell me what ordering
guarantees I can rely on across the range of processors.
-- Jamie
-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
Please read the FAQ at http://www.tux.org/lkml/
This archive was generated by hypermail 2b29 : Fri Sep 15 2000 - 21:00:15 EST