On Tue, 31 Oct 2000, Jeff V. Merkey wrote:
> [...] These types of optimizations are possible when people have
> acccess to Intel Red Cover documents, [...]
optimizing away AGIs has been documented by public Intel PDFs for years:
[...] Since the Pentium processor has two integer pipelines, a register
used as the base or index component of an effective address calculation
(in either pipe) causes an additional clock cycle if that register is the
destination of either instruction from the immediately preceding clock
cycle. This effect is known as Address Generation Interlock (AGI).
(ditto for the p6 core CPUs), and GCC (IIRC) tries to avoid AGI conflicts
as much as possible. (and this kind of stuff belongs into the compiler)
Ingo
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This archive was generated by hypermail 2b29 : Tue Oct 31 2000 - 21:00:31 EST